SU485392A1 - Digital Time Discriminator - Google Patents

Description

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i The invention relates to radio engineering and can be used in radio metering technology and in automatic control systems.

Digital temporal discriminators are known that contain a trigger, AND, OR circuits, and a pulse counter, which determine the delay time of the signal under investigation relative to the gate pulse.

However, when operating in the conditions of interference, a significant mismatch error appears, which, if removed, requires considerable complexity in the design of heading-i. nator.

The proposed device differs from the known one in that it is equipped with an additional counter and an adder, one input of which is connected to the output of an additional counter, and the other to the output of the main counter, one input of the additional counter is connected to the output of the OR circuit, and the other is connected to the output two-input circuit AND, the first Bxoffcbi of the trigger and the OR circuit is supplied with a gated signal, and their second inputs and one

the main counter input is a pulse of the start of the rtrob, the second input of the main counter is tied to the output of the three-input circuit, And, the days the inputs of both schemes And are connected to the clock output signal, and the others are input to the gate pulse. This made it possible to improve the accuracy of the measurement in the conditions of interference and simplify the device's configuration.

i The drawing shows a block diagram of the proposed digital time discriminator.

i Input 1 of the gate start pulse connected to the inputs of trigger 2 of the circuit OR 3 and 4. The input of 5 clock pulses is connected to one input of the three-input circuit | d 6 and two-input circuit AND 7. The input 8 of the gated signal is connected to other inputs of the OR circuit 3 and trigger 2 Gate 9 of the gate is connected to other inputs of the three-input circuit AND 6 and two-input circuit AND 7, the output of which is connected to one input of an additional counter 10, the output of which is connected to one input of the rummator 11, the second input of which is connected 3448

not with the output of the counter .4,. The output of the trigger 2 is connected to the third; VX) .drm circuit AND 6, the output of which is connected; BXi iJC) M counter 4. The output of the OR circuit 3 is connected to the second input of the auxiliary -; ; etchik 1O.

The discriminator works as follows.

The pulse of the strobe beginning from the input 1, the pulse counter 4 is put in the zero state, the counter 10 - in: the state corresponding to the number equal to the strobe duration in cycles, and the trigger 2 in the state at which its output voltage supplied on circuit And 6, together with the gate, also supplied to circuit 6, allows the passage of clock pulses from input 5 through circuit And 6 to the counter of clock pulses 4.

Counter 4 starts the incremental pulse count. From the beginning of the gate scheme And 7

transmits clock pulses to counter 10, which counts down pulses. The gated signal arriving at input 8 is two normalized pulses, the distance between which determines the width of the gated signal. The first input peak of the signal pulse or interference from input 8, which coincides with the strobe, triggers trigger 2, with the result that the flow of clock pulses to counter 4 stops. At this point, a number corresponding to the time, expressed in ticks from the beginning of the strobe to the first normalized signal pulse or interference, coinciding with the strobe is accumulated on the bead4. Each normalized pulse of a signal or interference matched with a strobe passes through the logic circuit OR 3 and sets an additional counter 10 to a state corresponding to a number equal to the duration of the strobe expressed in tact. After any such installation, the counter 10 conducts within the strobe a countdown of clock pulses sent to it from the scheme 7. At the end of the strobe on the additional counter 10 will be recorded a number corresponding to the distance expressed in cycles from the beginning of the strobe to the last of the normalized pulses. s signal or noise, matched with strobe. The adder 11 forms a half-sum of the readings of counters 4 and 10, which, after the end of the strobe, is numerically equal to the distance, expressed in cycles, from the beginning of the strobe to the middle of the gap between the first and last of the normalized signal pulses or interference, which coincided with the strobe. This half-sum is the output of the discriminator error (mismatch). It is used at any time after the end of the gate. The error signal taken directly from the summatr in the number system on the basis of which counters 4, 10 and the adder (for example, binary) are constructed. If necessary, the received error signal is then converted into any convenient form for its use.

Subject invention

The digital time discriminator, coaoj trigger, two-input and three-input AND circuits, one input of which is connected to the trigger output, the OR and HATCH circuitry, characterized in that, in order to improve the measurement accuracy in terms of interference and simplify the design, it is equipped with an additional counter and an adder, one input of which is connected to the output of the additional counter, and the other to the output of the main counter, one input of the additional counter is connected to the output of the OR circuit, and the other is connected to the output of the two-input circuit AND, the first the trigger and OR circuit moves the gated signal, and their second inputs and one input of the main counter receive a pulse of the start of the gate, the second input of the main counter is connected to the output of the three-input circuit AND, one of the inputs of both schemes AND is connected: to the clock input, and other strobe pulse input.

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