SU961140A1 - Pulse recurrence rate to code integrating converter - Google Patents

Description

The invention relates to measuring equipment and is intended for use in automation systems, in the measuring and computing systems, in particular for coupling frequency sensors with digital If we subtract ⁵ to computational machine.

A known converter of the pulse repetition rate into a code constructed on the basis of counters with switching devices at the input, which produce a pulse count during a reference time interval [1}.

Its drawback is the low ₁₅ precision.

The closest to the invention in technical essence is a converter containing the first and second counters, a code rewriting unit, 20 a memory register, a control unit, a clock generator connected with its output to the distribution control input.

block, which includes a counting trigger and two elements And [2].

A disadvantage of the known device is that it may be an error when switching the distribution block.

If the moment of switching the distribution block occurs during the pulse, then the same pulse can be received at the input of one counter, and the rest of the time after switching, it will be at the input of another counter. In this case, the same pulse will be counted twice, i.e. an error will appear.

The aim of the invention is to increase the accuracy of the conversion by eliminating the specified error.

This goal is achieved by the fact that in the integrating converter of the pulse repetition rate into a code containing a clock generator, the outputs of which are connected to

Control unit input and control

96114ο 4 inputs of the distribution block, the first and second outputs of which are connected respectively to the first and second inputs of the code coding block, the control input of which is connected to the $ first output of the control block, the installation inputs of two counters and the control input of the memory register, the information input of which is connected to the output the census block to · yes, the third and fourth outputs of the distribution block are connected to the counting inputs of the first and second counters, respectively, the outputs of which are connected to the inputs of the block e is the Census codes administered two monostable, two AND gates, RS-trigger, four differentiating circuits and four diodes, the direct and inverse outputs of the flip-flop Jr. different 'number of the first counter ₃₀ are connected respectively through the series-connected first differentiating circuit and a diode, and through a series-connected second differentiating circuit ₂₅ and a diode to the input of the first one-shot, the output of which is connected to the first input of the first element And, direct and inverse outputs of the trigger of the least significant discharge of the second counter respectively, through a third differentiating circuit and a diode connected in series and a fourth differentiating circuit and a diode connected in series to the input _{35 of the} second one-shot, the output of which is connected to the second input of the first element And, the third input of which is connected to the second output of the control unit, and the output to R - RS- ₄₀ input of a trigger, the S-input of which is connected to the input bus and the first input of the second And element, and the direct output - to the second input of the second And element, whose output is connected to the information _<5 dividing block.

In FIG. 1 is a functional diagram of an integrating converter of the pulse repetition rate into a code ·) in FIG. 2 is a stress diagram. ^so

Integrating the pulse repetition frequency converter to the code 1 comprises a first and second counters 2, 3 code block census storage register 4, a control unit 5, a generator ⁵⁵ Torr 6 clock pulses, its output connected to the control input of the junction block 7, comprising a counting trigger 8, and elements Y 9 and 10, the first 11 and second 12 single vibrators, differentiating circuits 13 “16, diodes, 17” 20, triggers 21 and 22 of the lower order, respectively, of the first 1 and second 2. counters, element And 23, RS-trigger 24, element And 25 and bus 26 of the input signal 27.

The converter operates as follows.

At a certain point in time, the first counter 2 is reset by command from the control unit 5, and the state of the second counter corresponds to the number of pulses received at its input. At this moment, the next clock pulse comes (Fig _; 2 a) from the generator 6, which translates the counting trigger 8 into a single state (RS-trigger 24 is also in a single state). The input pulses (Fig.2d) are fed through the input bus 26 to the first input of the And 25 element. Since a single signal arrives at the second input of the And 25 element, the pulses pass to the information input of the distribution block 7, the input pulses are hereinafter referred to as the first inputs of the elements Both 9 and Yu. Since a single signal from the direct output of the counting trigger 8 is applied to the second input of the And 9 element, the input pulses pass to the counting input of the first counter 1 (Fig.2d) and do not pass to the output of the And 10 element, to the second · input which is fed a logical zero signal with inverse the second output of the counting trigger 8. At the command from the control unit 5, submitted to the code rewriting unit 3 (Fig.2b), the code from the counter 2 is transferred to register 4. The next command (Fig.2c) from the control unit 5 resets the second counter 2. The first counter 1 counts the input pulses until the next clock pulse arrives, which transfers the counting trigger 8 to the opposite (zero) state. Further, the process is repeated, only the input pulses arrive at the counting input of the second counter 2 (Fig.2 e),. the second counter operates in the summing mode, and the first stores the accumulated code for transmission to the output register, i.e. to the output of the converter.

Each time the trigger of the lower order of the first counter is triggered, 5 961140 6 chic 1, the voltage from its direct and inverse outputs (Fig. 2 g, and) is differentiated by circuits 13 and T4, and each the first positive front from their inputs alternately through diodes 17. and 18 passes to the input of the first one-shot 11 (Fig. 2 m), at the output of which there is a pulse (Fig. 2p) with each rollover of the trigger 21 of the least significant discharge of the first counter 1 .· YU

Similarly, with each rollover of the trigger 22 of the lower order of the second counter 2, a pulse appears at the output of the second one-shot (Fig.2p). fifteen

The voltage from its direct and inverse outputs (Fig. 2 k, l) is differentiated by circuits 15 and 16, and each positive front from their outputs alternately passes through diodes -19 and 20 to the input of a single-shot 12 (Fig. 2n), at the output which there is an impulse at each rollover of the trigger 22 of the lower order of the counter 2 (fig.2p). 25

If the trailing edge of the clock pulse coincides with the input pulse (pulse 27 in FIG. 2d), this input pulse arrives at the inputs of both counters (FIG. 2e, e). up to Triggers 21 and 22 of the lower order of both counters work almost simultaneously and therefore both single-shots 11 and 12 work. The duration of the input pulses of one- ₃₅ vibrators is selected to be longer than the duration of the input pulse, but less than the minimum period of the input pulses. Therefore, the pulses arriving at the first and second inputs ₄₀ of the And 23 element partially coincide in time and an impulse appears at the output of the And 23 element (Fig. 2 c), a single signal is always sent to the third input of the And 23 element, except for ₄₅ cases, discussed below. The pulse from the output of the element And 23 puts the RS-trigger 24 in the zero state, as a result of which the inhibit signal is supplied to the input of the second element And 25. Therefore, the next input pulse from the bus 26 through the And 25 element does not pass to the corresponding counter, due to which the necessary error correction is obtained due to double counting by two pulse counters 27 (Fig. 2d). A pulse that does not reach the counters, however, is supplied to the S-input of the RS-flip-flop 24, which is brought into a single state by the trailing edge of the pulse, opening the And 25 element for the passage of the next input pulses.

The simultaneous operation of the single vibrators 11 and 12, in addition to the case considered, is also possible at the time of zeroing one of the counters by a pulse from block 5 (Fig.2c). To prevent the passage of one pulse, the And 23 element in this case is blocked by supplying its third input with a zero signal the output of the control unit 5, which is formed with the necessary overlap in time of the zeroing pulse (Fig. 2c, the pulses are shown with a dashed line).

Compared with known devices in which the indicated error is eliminated by an appropriate choice of signal parameters (a sufficiently small value of the pulse duration, an increase in the steepness of the edges, etc.), and the possibility of double pulse counting still remains, the proposed device uses the feedback principle - the fact is established incorrect operation of the meters and the necessary correction is made. Therefore, the invention without stricter requirements for the elements, i.e. while reducing cost, improves conversion accuracy.

Claims (2)

(S) INTEGRATING CONVERTER OF FREQUENCY OF FOLLOWING PULSES IN THE CODE The invention relates to measurement technology and is intended for use in automation systems, measurement and computing systems, in particular for coupling frequency sensors to a digital computer. A pulse frequency converter is known and a code constructed on the basis of counters with switching devices at the input, which produce a counting of pulses during the reference time interval. The disadvantage of it is low accuracy. The closest to the invention of the technical nature is a converter comprising first and second counters, a code rewriting unit, a memory register, a control unit, a clock pulse generator, connected by its output to a control input of a distribution unit including a counting trigger and two elements AND 2 . A disadvantage of the known device is that it is possible error when switching the distribution unit. If the moment of switching of the distribution block occurs during the action of a pulse, then the same pulse can arrive at the input of one counter, and at the rest of the time after switching it will turn out to be at the input of another counter. In this case, the same impulse will be counted twice, i.e. by Wits error. The aim of the invention is to improve the accuracy of the conversion by eliminating the indicated error. The goal is achieved by integrating a pulse following frequency converter into a code containing a clock generator, the outputs of which are connected to the control unit 0 INPUT and the control unit 396 of the distribution block whose first and second outputs are connected to the first and second blocks of the census, respectively. the code, the control input of which is connected to the first output of the control unit, the installation inputs of two counters and the control input of the memory register, the information input of which It is connected to the output of the census block, the third and fourth outputs of the distribution block are connected to the counting inputs of the first and second counters, respectively, the outputs of which are connected to the inputs of the code rewriting block, two single vibrators, two And, RS flip-flop elements, four differentiating circuits and four diodes, with the direct and inverse outputs of the low-order trigger of the first counter connected respectively through a series connected first differentiating circuit and a diode and connected through a series connected the second differentiating circuit and the diode to the input of the first one-shot, the output of which is connected to the first input of the first element I, the direct and inverse outputs of the low-order trigger of the second counter: connected, respectively, through a series connected third differential circuit and a diode and through serially connected quarters the differentiating circuit and the diode to the input of the second one-shot, the output of which is connected to the second input of the first element I, the third input of which is connected to the second output of the control unit, and the output - to the R input of the RS trigger, the S input of which is connected to the input bus and the first input of the second element I, and the direct output to the second input of the second element I whose output is connected to the information input of the distribution unit. FIG. Figure 1 shows the functional for the integrating transform transform of the pulse frequency pulse bodies in the CODE} on f.ig. 2 is a voltage chart. The integrating pulse-to-code-to-code converter contains the first t and second 2 counters, a code rewriting unit 3, a memory register 4, a control unit 5, a clock pulse generator 6 connected by its output to a control input of a distribution unit 7, 4 including counting trigger 8, and elements 9 and 10, the first 11 and second 12 single vibrators, differentiating circuits, diodes, triggers 21 and 22 low-order bits, respectively, of the first 1 and second 2 counters, element I 23, RS flip-flop 2k , element 25 and bus 2b of the input signal 27. The Converter operates as follows. At a certain point in time, the first counter 2 is reset by a command from control unit 5, and the state of the second counter corresponds to the number of pulses received at its input. At this moment, another clock pulse arrives (FIG. 2 e) C of generator b, which converts counting trigger 8 into a single state (the RS-flip-ger is also in a single state). The input pulses (Fig. 2d) are fed through the input bus 2b to the first input of the And 25 element. Since the second input of the And 25 element receives a single signal, the pulses pass to the information input of the distribution block 7, the input pulses are then fed to the first inputs of the elements Both 9 and 10. Since the second input of the element And 9 is given a single signal from the direct output of the counting trigger 8, the input pulses pass to the counting input of the first counter G (Fig. 2d and do not pass to the output of the element 10, the second input is a logical zero signal with an inv rsnogo countable output latch 8. On command from the control unit 5, filed on census block 3 code (2b code from the counter 2 is transferred to the register. The next command (in Figure 2 by the control unit 5 produces the second reset counter 2. The first counter 1 counts the input pulses until the next clock pulse arrives, which transfers the counting trigger 8 to the opposite (zero state. Then the process repeats, only the input pulses arrive at the count input of the second counter 2 (Fig. 2e), the second the counter operates in the summing mode, and the first stores the accumulated code for transmission to the output register, i.e., to the output of the converter. Each time the low priority trigger 21 of the first counter 1 triggers, the voltage from its direct and inverse outputs (FIG. . 2 g, i) is differentiated by chains 13 and m4, and each positive front from their inputs alternately through diodes 17. and 18 passes to the input of the first single-oscillator 11 (Fig. 2 m), at the output of which an impulse ( fig. 2p) each time the trigger 21 of the lower bit of the first counter 1 flips over. Similarly, with each tip of the 22 low bit of the second porq of the counter 2 flips up, the output of the second single-vibrator appears on the second (fig, 2p). and inverse outputs (Fig. 2k, l) the chains are differentiated; 15 and 1b and each positive front from their outputs alternately through diodes -19 and 20 passes to the input of the one-shot 12 (figure 2, the output of which is a pulse at each tipping over of the trigger 22 low-order counter 2 (figure 2p) In case of a falling edge of the clock pulse with the input pulse (pulse 27 in Figure 2d), this input pulse enters the inputs of both counters (Figure 2d, e). The triggers 21 and 22 of the lower order of both counters almost simultaneously trigger and therefore both one-shot 11 and 12, Duration the input pulses of the one-shot are chosen longer than the input pulse, but less than the minimum follow-up period of the input pulses.Therefore, the pulses arriving at the first and second inputs of AND 23 partially overlap in time and an pulse appears at the output of AND 23 (Fig.2 ), the third input of the And 23 element is always given a single signal, except for the case discussed below.The impulse from the output of the And 23 element transfers the RS flip-flop 2k to the zero state, as a result of which the inhibiting sy drove Therefore, the next input pulse from bus 2b through element 25 does not pass to the corresponding counter, due to which correction of the error due to double counting with two pulse counters 27 is necessary (fig.2d). The impulse that did not hit the counters, however, arrives at the S input of the RS flip-flop, which is driven back by the pulse front to the unit state, opening element 25 for passing the following input pulses. Simultaneous operation of one-shot 11 and 12, in addition to the examined case, it is also possible at the moment of zeroing one of the counters with a pulse from block 5 (Fig. 2b). To prevent one impulse from being passed, the element 23 in this case is locked by feeding its third input zero signal the output of the control unit 5, which forms, with the necessary overlap in time of the zero pulse (Fig. 2c, the pulses are shown in dashed lines). Compared with the known devices, in which the elimination of the specified error is carried out by appropriate selection of the signal parameters (the pulse duration is quite small, the increase in the steepness of the fronts, etc.), the possibility of double pulse counting still remains, in the proposed device the feedback principle is set the fact of incorrect operation of the counters and the necessary correction is made. Therefore, the invention without strict requirements to the elements, i.e. while reducing the cost, it improves conversion accuracy. The invention integrates a pulse frequency converter into a code comprising a clock generator, the outputs of which are connected to the input of the control unit and the control input of the distribution unit, the first and second outputs of which are connected respectively to the first and second inputs of the code rewriting unit, the control input of which is connected with the first output of the control unit, the installation inputs of two counters and the control input of the memory register, whose information input is connected to the output Lok code census, third and fourth outputs of the distribution unit connected to the counting inputs of the first and second counters, the outputs of which are connected to inputs of codes census block, characterized