SU1156070A1 - Device for multiplying frequency by code - Google Patents

Device for multiplying frequency by code Download PDF

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Publication number
SU1156070A1
SU1156070A1 SU833657413A SU3657413A SU1156070A1 SU 1156070 A1 SU1156070 A1 SU 1156070A1 SU 833657413 A SU833657413 A SU 833657413A SU 3657413 A SU3657413 A SU 3657413A SU 1156070 A1 SU1156070 A1 SU 1156070A1
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SU
USSR - Soviet Union
Prior art keywords
input
output
trigger
inputs
frequency
Prior art date
Application number
SU833657413A
Other languages
Russian (ru)
Inventor
Михаил Дмитриевич Генкин
Андрей Павлович Кириллов
Геннадий Федорович Пешков
Олег Борисович Скворцов
Петр Петрович Седулин
Original Assignee
Институт Машиноведения Им.А.А.Благонравова
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Application filed by Институт Машиноведения Им.А.А.Благонравова filed Critical Институт Машиноведения Им.А.А.Благонравова
Priority to SU833657413A priority Critical patent/SU1156070A1/en
Application granted granted Critical
Publication of SU1156070A1 publication Critical patent/SU1156070A1/en

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Abstract

COMPETITION FOR MULTIPLICATION OF THE FREQUENCY ON A CODE, containing a clock pulse generator, two controllable dividers, a counter and a register, the output of the clock pulse generator is connected to the information inputs of the first and second controlled dividers, the control inputs of which are connected respectively to the input of the multiplication factor setting the device and the output of the register, the information inputs of which are connected to the corresponding outputs of the bits of the counter, the counting input of which is connected to the output of the first deltap control, the cycle The register input is connected to the reset input of the counter and is the frequency reference input of the device whose output is connected to the output of the second frequency divider, characterized in that, in order to improve accuracy by ensuring that the frequency of the input signal is controlled within acceptable limits, it contains five figger , six elements And, two elements of the prohibition, four elements OR, and the frequency setting input of the device is connected to the counting input of the first trigger, the first inputs of the first, second and third elements AND, the information The inputs of the first and second prohibition elements, the input of the second controlled delntel, the reset input and the direct output of the first trigger are connected respectively to the output of the first absorber and the second input of the first element, whose output is connected to the input of the second trigger and the first input of the first element OR, the second input of which is connected to the reset input of the second trigger and the transfer output of the counter, the outputs of the higher bits of which are connected With the corresponding inputs of the fourth element And and the second element nta OR, the inverse output of which is connected to the installation input of the third trigger, the second input of the third element AND and the control input of the first prohibition element, the output of the first element OR is connected to the installation input of the fourth trigger, the reset input of which is connected to the reset input of the device, the error output of which connected to the output of the fourth trigger and the first input of the fifth element I, the output and second input of which are connected respectively to the output of the device error type and the direct output of the second trigger, the output the fourth element I is connected to the reset input of the third trigger, the second input of the second element AND and the controlled input of the second prohibition element, the outputs of the second and third elements AND are connected, respectively, with the first AND second inputs of the third OR element, the output of which is connected with the installation input of the fifth trigger, the outputs of the first and second prohibition elements are connected to the corresponding inputs of the fourth OR element, the output of which is connected to the reset input of the fifth trigger, the output of which is connected to the first input th AND gate and is output warning signal device, a third latch output is connected to the second input of the sixth AND gate, whose output is the output signal of the form u eduprezhdensh1 device.

Description

The invention relates to computing and can be used in computing devices and automatic control systems for converting data in a frequency-pulse code. A device for multiplying a frequency by a code comprising two counters and a controlled divider 1 are known. A disadvantage of the known device is concluded with the lack of control of the input frequency. It is also known a device for multiplying a frequency with a code containing a clock pulse generator, two controlled dividers, a counter, a register, and the output of the generator of so-called pulses is connected to the information inputs of the first and second controlled dividers, the control inputs of which are connected, respectively, to the input of the coefficient multiplying the device and the register output, the information inputs of which are connected to the corresponding outputs of the counter bits, the counting input of which is connected to the output of the first controlled de The clock register input is connected to the reset input of the counter and is the frequency input of the device whose output is connected to the output of the second frequency divider 2. However, the lack of control over the output frequency of the input signal beyond the allowable limits in this device can lead to nondiagnosis x errors in functioning. The purpose of the invention is to improve accuracy by ensuring that the frequency of the input signal is within acceptable limits. This goal is achieved in that the device for multiplying the frequency with a code containing a clock pulse generator, two controlled dividers, a counter and a register, the output of the clock pulse generator connected to the information inputs of the first and second controlled dividers, the control inputs of which are connected respectively to the job input the multiplication factor of the device and the output of the register, the information inputs of which are connected to the corresponding outputs of the bits of the counter, the counting input of which is connected to the output of The controlled divider, the clock input of the register is connected to the reset input of the counter and is the frequency reference input of the device whose output is connected to the output of the second frequency interval, contains five triggers,. six AND elements, two prohibition elements, OR four elements, and the input of the task is often connected to the first, second and third AND counting inputs, information inputs of the first and second prohibition elements, the reset input of the second controlled divider, the reset input and direct the output of the first trigger is connected respectively to the output of the first controlled divider and the second input of the first element AND, the output of which is connected to the installation input of the second trigger and the first input of the first OR element, the second input of which one with the reset input of the second trigger and the output of the counter prekos, the outputs of the higher bits of which are connected to the corresponding inputs of the fourth AND element and the second OR element, the inverse output of which is connected to the installation input of the third trigger, the second input of the third AND element and the control input of the first the prohibition element, the output of the first element OR is connected to the setup input of the fourth trigger, the reset input of which is connected to the reset input of the device, the error output of which is connected to the direct output of the fourth t the trigger and the first input of the fifth element I, the output and the second input of which are connected respectively to the output of the device error type and the direct output of the second trigger, the output of the fourth element I is connected to the reset input of the third trigger, the second input of the second element And and the control input of the second element the prohibition, the outputs of the second and third elements And are connected respectively with the first and second inputs of the third element OR, the output of which is connected to the input of the installation of the fifth trigger, the outputs of the first and second elements of the prohibition with the corresponding inputs of the fourth OR element, the output of which is connected to the reset input of the fifth trigger, the output of which is connected to the first input of the sixth AND element and is the output of the device’s warning signal, the third trigger output is connected to the second input of the sixth AND element, the output of which is output of the device alarm alert type. The drawing shows a block diagram of a device for multiplying a frequency by a code. The device for multiplying the frequency by the code contains 1 clock pulse generator, first controlled divider 2, counter 3, register 4, second controlled divider 5, device output 6, device frequency setting input 7, device multiplication factor setting input 8, triggers 9 -13, elements AND 4-G9, elements OR 20-23, elements. prohibitions 24 and 25, error outputs 26-29, type of error, warning signal and type of warning signal, device reset input 30. The device for multiplying the frequency by the code works as follows. Before the operation of the signal supplied to the input 30, the device is reset. In this case, the trigger 12 is in the zero state, and at its direct output a zero signal arrives at the output 26, which indicates the absence of a fault. The input frequency signal is fed to the input 7 and the first pulse provides a reset of the counter 3 and the controlled divider 5. The code N, to which the frequency signal is needed, is fed to the input 8. The controlled divider 2 provides the division of the output signal of the generator 1 fn N and pulses From the output of the controlled divider 2, a counter 3 arrives, which over the time between the input frequency pulses equal to 1 / f, will fix the code M --V. The next impulse of the input frequency on the leading edge of the code M is rewritten in register 4, and on the falling edge of the counter 3 and the controlled divider 5 are reset to zero. Divider 5 provides a division of the frequency f.f by M, i.e. forms at the output 6 a signal with a frequency f - N - f. On the falling edge of the first pulse of the input frequency, the trigger 9 is switched to one state, and the pulse from the output of the controlled divider 2, the trigger 9 is set to the zero state. If the frequency of the input pulses exceeds the permissible limit, during the time between the input frequency pulses there will not be a single pulse at the output of the controlled divider 2 and as soon as the second pulse appears at input 7, trigger 9 will be in one state. In this case, the input frequency pulse will pass through the elements AND 14 and OR 20, setting trigger 12 to one, which corresponds to the signal going out of acceptable limits, as evidenced by the appearance of a single logical signal at output 26. At the same time, trigger 10 is set by the same pulse to a single state, which indicates that f is greater than the maximum allowed, which is indicated by a single logic signal at output 27. If f is smaller than the minimum allowable value, during the time between the frequency pulses of the pr counter 3 will overflow, the signal from the transfer output of which trigger 12 will also be set to one, and trigger 10 to zero, which will cause the appearance of single and zero signals at outputs 26 and 27, respectively, indicating the presence and type of malfunction devices. The state indicating the presence of an error is saved until the operator or an external device sets the reset signal at input 30. If the pulse frequency approaches the minimum or maximum permissible value, all the leading bits of counter 3 will be in the single or zero state, respectively, which leads to to the appearance of single signals at the outputs of the elements, respectively, AND 17 or OR 21, setting trigger 11 to zero or one state, respectively. In this case, the next pulse of the input frequency trigger 13 is set to a single state, which causes the appearance of a single signal at output 28, which indicates that f approaches the boundary values. The form of this limit value is fixed by the signal at output 29. If f further changing, moving away from the boundary values by following pulses arriving at input 7 and passing through the OR element 23, the trigger 13 is set to the zero state and the approach signal to the permissible rpaimue disappears. The positive effect of the invention with respect to the prototype is that the proposed device provides both control over the {{approximation of the frequency of the reference pulses to the allowable limits) and control of the frequency output beyond the allowable limits, which allows eliminating unreported errors and taking timely measures control of the source of reference pulses.

Claims (1)

  1. and the output of the register, the information inputs of which are connected to the corresponding outputs of the bits of the counter, the counting input of which is connected to the output of the first control of the divider, the clock input of the register is connected to the reset input of the counter and is the input of the frequency reference of the device, the output of which is connected to the output of the second frequency divider, characterized in that, in order to improve accuracy by ensuring that the input signal frequency is within acceptable limits, it contains five triggers, six AND elements, two elements per PETA, four OR gate, wherein input. setting the frequency of the device is connected to the counting input of the first trigger, the first inputs of the first, second and third elements And, information inputs of the first and second elements of the ban, the reset input of the second ; controlled divider, reset input and direct output of the first trigger are connected respectively to the output of the first control, removable divider and the second input of the first AND element, the output of which is connected to the installation input of the second trigger and the first input of the first OR element, the second input of which is connected to the reset input of the second trigger and a counter transfer output, the high-order outputs of which are connected to the corresponding inputs of the fourth AND element and the second OR element, whose inverse output is connected to the installation input third about the trigger, the second input of the third element AND n the control input of the first inhibit element, the output of the first OR element is connected to the installation input of the fourth trigger, the reset input of which is connected to the reset input of the device, the error output of which is connected to the direct output of the fourth trigger on the first input of the fifth element And , the output and the second input of which are connected respectively to the output of the type of error of the device and the direct output of the second switch а a > the output of the fourth element And is connected to the reset input of the third trigger, the second -> input the ode of the second AND element and the control input of the second inhibit element, the outputs of the second and third AND elements are connected respectively to the first I by the second inputs of the third OR element, the output of which is connected
SU833657413A 1983-10-28 1983-10-28 Device for multiplying frequency by code SU1156070A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU833657413A SU1156070A1 (en) 1983-10-28 1983-10-28 Device for multiplying frequency by code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU833657413A SU1156070A1 (en) 1983-10-28 1983-10-28 Device for multiplying frequency by code

Publications (1)

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SU1156070A1 true SU1156070A1 (en) 1985-05-15

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Application Number Title Priority Date Filing Date
SU833657413A SU1156070A1 (en) 1983-10-28 1983-10-28 Device for multiplying frequency by code

Country Status (1)

Country Link
SU (1) SU1156070A1 (en)

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
1. Авторское свидетельство СССР N 634277, кл. G 06 .F 7/52, 1977. 2. Авторское свидетельство CCCPN 580555, кл. G 06 F 7/52, 1976 (протопш). *

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