SU1709528A1 - Converter of code to period of iteration of pulses - Google Patents

Abstract

The invention relates to computing, in particular, to data conversion and transmission devices. The purpose of the invention is to increase the reliability of the converter by simplifying it. This is achieved by those. that in the code converter during the pulse repetition period, containing a subtracting counter with input code buses, a trigger, an element I. the input and output bus and the reset bus, the nth information input of the subtractive counter is connected to the "O constant" bus, and its pth the output is with the installation input of the trigger unit, the input of the zero input of which is connected to the counting input of the detracting counter and is the input bus, the direct output of the trigger is the output bus, and the inverse output is connected to the first input of the element I. Its second input is a tire with throw, and the output ~ is connected to the input of the write resolution of the subtractive counter. 2 Il.

Description

The invention relates to computing technology, namely, data conversion and transmission devices, and can be used to convert parallel binary code 8 pulse repetition period.

The aim of the invention is to increase the reliability of the converter by simplifying it.

Figure 1 shows a block diagram of a code converter during a pulse repetition period; Fig. 2 shows a sequence diagram of the operation of a converter having a four-bit counter for the K-3 code.

The code converter in the pulse repetition period contains the subtractive counter 1. whose information inputs

Do. DI Dn-1 are input bus 2

code, the input 3 of the higher bit On is connected to the Bus Constant O, and its output 4 (Qn) is connected to input 5 setting of the RS trigger unit 6. Input 7 of the zero setting of which is connected to the input bus 8 and counting input 9 of the counter 1.

In addition, the converter contains an output bus 10. An AND element 11 and a reset bus 12, an input 13 for recording the counter 1.

The principle of operation of the proposed converter is the cyclic repetition of the counting by the subtractive counter 1 from the preset state of the counter specified by the input binary code K via bus 2 and corresponding to the beginning of the cycle

conversion to the overflow state of the counter corresponding to the end of this cycle. Decoding of the overflow state of the counter is performed only by the state of the high order of the counter due to presetting the On input of the most significant bit to the constant state of logical O and excluding, thus, acting on the input 3 of the input code K. The overflow state of the counter cokes the RS trigger 6 in the unit state in which it exists during the existence of the latter in the cycle of the input pulse and which is removed at the end of the action of the latter in the cycle of the pulse. The single state of the RS flip-flop forms the resolution of writing to the counter 1 of the outer code K, after which a new analogous conversion cycle begins.

Consider the operation of the converter for the case of a four-bit subtractive counter 1 and the numerical value of the K 3 code. The counter thus has inputs Do, Di, Da, Da and outputs Qo, Q, Qa, Oz. The initial signal Reset with a logic level O arrives at bus 12, passes through AND 11 (regardless of the second input of AND) at its output and appears at input 13 of recording resolution (V) of counter 1. At the same time, bus 8 has a level logical o {see fig.i, in. bus 8 and bus 3 from tooc to too).

When the logic level O at the input 13 of the counter occurs, the installation and retention of the counter 1 in the state,,, and K 3 m takes priority.

With Sa-l and O on bus 8, we have at inputs 5 and 7 of trigger b, respectively, 5 1 and R 0. These signals unambiguously set trigger 6 to the state From O, QT 1 in the original STATUS.

After removing the signal Reset on bus 12 (transition np logic level 1) and in the absence of positive input pulses on bus 8, S 1 and R O are kept at the inputs of trigger 6. The converter is in the initial state and is ready for operation. After this, the occurrence of the first positive input pulse on bus 8 and at input 9 of the counter transfers subtractive counter 1 to the state 0 0. 01 - 1, Qa ° O, Oz O, while the state From - O does not change (see figure 2, the moment tn). Similarly, pass the 2nd and 3rd input pulses, reducing the exit code O each time by 1 on the leading edge of the positive pulse.

The fourth input pulse puts the counter in the overflow state QO Oi Oa Oz 1 (see Fig. 2, time tn). Inverse output 4 senior bits oz

enters the state Oz 0. Thus, at the moment of arrival of the fourth pulse at the input 7 of the RS-flip-flop, the logic level 1 is found, and at the input 5 - the logic level O. Therefore, at the time and (see Fig. 2)

The RS flip-flop goes into a state in which QT 1, From 0. Next, the logic level O from the inverse output From RS trigger, passing through the element 11 to input 13, sets the counter to the initial

state in a similar way. While OO 1, Oi 1, Oa O, Oz O (see figure 2, the moment to). The state set from the moment of arrival of the 4th pulse From 1, the RS flip-flop retains even after the installation of the counter into the initial

state, until the end of the whole 4th input pulse, since the logic levels 1 are at the inputs R and S R3-TpHrrepa 1. The state From 0, respectively, during the 4th pulse acts on the counter recording enable input 13, which ensures a stable preset (entering the K code) of the counter (see Fig. 2, the interval t4 is too). Then, from the moment too (see figure 2), a new work cycle begins.

converter

From the sequence diagram can be seen (see figure 2). that with K 3 Your 4TVh (K + 1) Those that corresponds to the law of transformation of the device. The analog converter is written for other numerical values of the K code and for the size of the subtracting counter.

Claims (1)

The invention of a code converter during a pulse repetition period containing a subtractive counter, n-1 information inputs of which are an input code bus, a trigger, an AND element, an input and output bus, a reset bus, characterized in that In order to increase the converter’s reliability by simplifying it, the nth information input of the downlink counter is connected to the Bus Constant O, and its -th exit is connected to the setup input; the trigger unit, the setup input zero of which is connected to the counting input of the down counter and is the input bus, the forward trigger output is the output bus, and the inverse output is connected to the first the input of the element is And, the second input of which is a reset bus, and the output is connected to the input of the write resolution of the subtracting counter. IG