SU402156A1 - PULSE DISTRIBUTOR - Google Patents

Description

one

The device can be used in computing, automation, systems for converting and encoding information.

Known pulse distributor with an odd number of outputs for aut. St. No. 189227, containing a two-contact trigger register and a clock trigger, in which the last register trigger through a delay circuit for a time shorter than the cycle duration, is connected to the counting input of the clock trigger.

Once per cycle of the work of the distributor, an additional transfer of the clock trigger between two clock pulses occurs, which leads to a reduction in the speed of the distributor by half as compared with the speed of the clock trigger.

The purpose of the invention is to increase the speed of the device.

The proposed pulse distributor is characterized in that the trigger of the last bit cell is connected to a zero output via a delay element for a time shorter than the cycle time, with one input of the fusion circuit and the diode anode, and with a single output with the input of the first register trigger unit, and the cathode of the diode are connected, respectively, with a counting input and a single output of the trigger cell of the first discharge.

The drawing shows a functional diagram of a device consisting of five triggers. The pulse distributor consists of register 1-5 triggers, clock trigger 6, delay element 7, coincidence circuit 8 and diode 9.

In the initial state, all the register triggers, except for one, are in the state "zero.

Let us assume for definiteness that at the beginning of operation, the unit is written in trigger 1, and zero in triggers 2-6. In this case, the circuit 8 and the diode 9 are blocked by a negative potential, which comes through the delay element 7 from the zero output of the trigger 5.

The first clock pulse from the output of 10 flip-flop 6 writes zero to flip-flop 1. When flashing a flip-flop from one to zero, flip-flop 2 records one. Next clock

impulse - from output 11 of trigger 6 rewrites the unit from trigger 2 to trigger 3. The last even clock pulse occurring on bus 10 rewrites the unit from the fourth (penultimate) trigger of the register to the fifth.

After the trigger 5 is set to one, after the delay time of the element 7, the coincidence circuit 8 is opened, and the diode 9 is displaced in the forward direction, resulting in the trigger 6

fixed at zero.

For the normal operation of the distributor, the delay time of the element 7 must satisfy the inequality

,

where Ti is the duration of the input pulses; TF - the duration of the trigger pulse;

T is the period of the following impulses.

The next input pulse, having passed through the open circuit 8, rewrites the unit from the last register trigger to the first one, and the state of the clock trigger 6 does not change. By the time of arrival of the next input pulse, the diode 9 is closed, and the clock trigger 6 can again work on the counting input.

Further, the distributor operates according to the described cycle.

In contrast to the pulse distributor by author. St. № 189227 where the duration of the pulses taken from the output of the last register trigger is different from the duration of the pulses on the other triggers by the value T - t

-G, In this distribution

This difference is equal to the duration of one edge of the trigger pulse 6.

If before the signal input of the circuit 8 to enter a delay element, this difference can be eliminated.

Subject invention

Pulse distributor by bus. St. No. 189227, characterized in that, in order to increase speed, the zero output of the last discharge cell trigger is connected via a delay element to one input of the coincidence circuit and to the anode of the diode whose cathode is connected to the single output of the clock trigger whose counting input is connected to the bus input pulses to another input of the coincidence circuit, the output of which is connected with the zero input of the trigger cell of the last bit, the unit output of which is connected to the single input of the trigger cell of the first bit.