SU1406790A1 - Variable-countdown frequency divider - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation devices, telemechanics and computer technology. The purpose of the invention, the speed increase, is achieved by additionally introducing a delay element 3 and a short pulse shaper 2 into the device. The device also contains an input bus 1 counting pulses, an auxiliary counter of 4 pulses, a main counter of 5 pulses, a decoder 6, a code writing unit 7 and a bus 8 of the division coefficient code. In the proposed divider, the effect of the delay when switching from counting mode to code writing mode is eliminated. The speed of the device depends only on the speed of the applied triggers in the first bits of both counters. The operation of the device is explained in the time diagrams provided in the description of the invention. 2 Il. (L

Description

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The invention relates to a pulse technique and can be used in automation devices, telemechanics and computer technology.

The purpose of the invention is to improve speed.

FIG. 1 shows the electrical structural diagram of the device; in fig. 2 - time diagrams for his work. The device contains an input bus 1 counting pulses, a short pulse shaper 2, a delay element 3, an auxiliary 4 and a main 15 5 pulse counters, a decoder 6, a code writing unit 7, a bus 8 of the division ratio code. Bus input

1connected to shaper input

2 short pulse, the output of which is connected to the input of the delay element 3, to the counting input of the main counter of 5 pulses and to one of the inputs of the decoder 6. The output of the element

3 delays are connected to the counting input of the auxiliary counter of 4 pulses. The inverse output of the auxiliary counter of 4 pulses is connected to the counting input input

The counting pulses going to the counting input of the counter 5 describe from it j the previously recorded code. When on the inverse outputs of the bits of counter 5, signals with level 1 appear, i.e. the counter 5 is set to the zero state, at the output of the decoder 6 a signal O appears at the trailing edge of the short counting pulse;

This signal sets at the inverse output of the last digit of counter 4, level O, prohibiting further passage of the counting pulses to the counting input of counter 5. At the forward output of the last digit of the counter 4, signal 1 appears that permits the passage of counting pulses into the counter 4 At the same time, the signal from the output of the decoder 6 through block 7 sets at the output of counter 5 a previously recorded code. The following counting pulses from the output of element 3 are passed to counting input 25 of counter 4. After two counting pulses pass into counter 4, the signal from the direct output of the last discharge prevents the counting pulses from passing to counting input 20

go counter 5 pulses. Vkod depshf-- 30 ka 4, and the signal 1 from the inverse output

The counting pulses going to the counting input of the counter 5 describe from it j the previously recorded code. When on the inverse outputs of the bits of counter 5, signals with level 1 appear, i.e. the counter 5 is set to the zero state, at the output of the decoder 6 a signal O appears at the trailing edge of the short counting pulse;

This signal sets at the inverse output of the last digit of counter 4, level O, prohibiting further passage of the counting pulses to the counting input of counter 5. At the forward output of the last digit of the counter 4, signal 1 appears that permits the passage of counting pulses into the counter 4 At the same time, the signal from the output of the decoder 6 through block 7 sets at the output of counter 5 a previously recorded code. The following counting pulses from the output of element 3 pass to the counting input of counter 4. After the passage of two counting pulses into counter 4, the signal from the direct output of the last discharge prevents the counting pulses from passing to the counting input of the counter

RATOR 6 is connected to the control input to the code block 7, to the setup input of the auxiliary pulse counter 4 in one state. The last output of the last bit of the auxiliary counter of 4 pulses is connected to the counting enable input of the same pulse counter. Bus 8 code division factor through the block 7 of the code entry is connected to the inputs of the installation code of the main counter 5 pulses. The outputs of the main counter 5 pulses are connected to the corresponding inputs of the decoder 6.

The device works as follows.

The input signal of the counting pulses is fed to the input of the imager 2, in which short pulses are formed. Suppose that the device is in the state when counter 7 uses block 7 to write the code of the division factor, with signal 1 at the count counter enable input, allowing the count, and counter O signal billing at the count counter 5 input. Signal 1 is present at the output of the decoder of torus 6.

five

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Yes, the last bit of counter 4 permits further passage of the counting pulses to the counting input of the counter 5. Next, the counting cycle is repeated. In order to eliminate the influence of the delay, during the overwriting of an ode in counter 5 (during one counting cycle), a certain number of pulses are passed that enter counter 4. More than two digits dp of counter 4 are impractical, since the time of two periods the input frequency is enough to write the code into the counter 5. The counters 4 and 5 to reduce the effect of delays operate in the subtraction mode, and the counter 4 can be performed according to a parallel transfer circuit. As can be seen from the timing diagram, the pulse duration (Fig. 2d) of writing the code at the output of the decoder 6 does not affect the speed of the device. If, even at the highest input frequency, its duration will be more than one period of the input frequency, the next incoming counting pulse to the input of the decoder 6 will shorten its falling edge. The shorter the impulse from the output is

The lower the delay time from the leading edge of the short pulse to the leading edge of the write resolution resolution of the code at the inverse output of the counter A, the faster the device performance. The delay time of the input pulse in element 3 is chosen to be equal to the sum of two delays, one of which is the delay time of the decoder 6, and the other is the delay time for setting the counter 4 to one state. As can be seen from FIG. 2, the trailing edge of the delayed pulse (Fig. 26) coincides with the pulse-firing pulse pulse front at the inverse output of counter 4, and the trailing edge of the shortened input pulse {Fig. 2a) at the output of the imager coincides with the pulse front (Fig. 2c) of the counting resolution on the inverse output of counter 4. This eliminates the effect of delays when switching the device from counting mode to code writing mode. The speed of the device depends only on the speed of the applied triggers in the first bits of their counters.

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Claims (1)

Invention Formula The frequency divider with a variable division factor, containing the main pulse counter, the installation inputs of which code are connected through the code writing unit to the division ratio code buses, the outputs with corresponding decoder inputs, an auxiliary pulse counter and an input bus that differs from speed increase, a delay element and a short pulse generator, the input of which is connected to the input pinnacle, are entered into it, the output - with the counting input of the main pulse counter, with an additional input through the delay element - with the counting input of the auxiliary pulse counter, the last output of which the last bit is connected to the counting input of the same pulse counter, the inverse output of the last bit — with the counting enable input of the main pulse counter, the installation input into the unit co- This is with the output of the decoder and with the control input of the code writing unit.