SU1265981A1 - Device for discriminating pulses - Google Patents

Abstract

The invention relates to a pulse technique. It can be used in automation, computing and measuring devices. The purpose of the invention is to expand the functionality achieved by dividing the input pulse sequence into two sequences. The goal is achieved by the introduction of new functional relationships. The device contains clock 1, 1, counter 2, D-flip-flop 3, output buses 5, 6, and 9, elements AND 4, 7, and information bus 8. The pulse sequence arriving at the data bus is divided into two pulse sequences, with On the output bus 6 this is the sequence of clock pulses, and on the bus 9 - a sequence of information pulses. 2 Il. (L ND 05 sd; about 00

Description

The invention relates to a pulse technique and can be used in automation devices, computing and measuring equipment.

The purpose of the invention is to extend the functionality by dividing the input pulse train into two sequences.

Figure 1 shows an electrical functional diagram of the device; 2 shows timing diagrams for his work.

The device contains a clock time I connected to the counting input of counter 2, the installation input of which is connected to the direct output of Dtrigger 3, and the first input of the first AND-4 element 4. The first output is connected to the first output bus 5, and the second output - to R- the input of the D-flip-flop 3, the C-input of which is connected to the second output bus 6 and the output of the second element NAND 7, and the inverse output to the first input of the second element NAND 7, the second input of which is connected to the information bus 8 and the second input the first element AND-NOT 4, the output of which is connected to the third output bus 9.

The device works as follows.

The information bus 8 generally receives a sequence of pulses, which has two components: a sequence of clock pulses and, offset from it by half a period, a sequence of information pulses, which is random in nature (Fig. 2a).

In the initial state at the direct output of the D-flip-flop 3 there is a low potential (fig.2b), and on the inverse - high potential (fig.2d). A nerve impulse arriving at the information bus 8 passes through the AND-HE 4 element (FIG. 26), and with its back front it sets a high potential on the forward output of the D trigger.

The next impulse, which is attached to the information bar, passes through the INE 4 element to the output pin 9 (Fig. 2e). The conversion factor of counter 2 and the frequency of clock pulses on tire 1 (fig.2i) are chosen so that the frequency of the pulses at the output of counter 2 (fig.2e) coincides with the frequency of the clock pulses, but they follow with a delay slightly less than the period of clock pulses the clock pulses are counted from the moment of the appearance of the permissive potential on its

setup input from the direct output of the D-flip-flop 3.

After the appearance of a pulse from the output of the counter 2, D-trigger 3 is set to the zero state and the next incoming

bus 5, a pulse is again allocated on the output bus 6. In the absence, for some reason, an overflow of pulses is generated on the input bus 8 of the next clock pulse on the output bus 5

(Fig. 2g), the number of which for a certain period of time indicates the reliability of the incoming information on the input bus 8 (Fig. 2a, the pulse shown by the dotted line).

The operation of the device does not depend on

which impulse comes through bus 8 first — an impulse of information or a clock frequency. The device automatically restores the switching of pulses along the output circuits by the first logical zero by 8 (no information pulse).

Thus, the sequence of pulses arriving at the information bus 8 is divided into two sequences of pulses, the sequence of clock pulses being allocated to the output bus B, and a sequence of information pulses at the output bus 9.

Claims (1)

Invention Formula A device for separating pulses, containing a pulse counter, a clock P1, information bus connected to the first input of the first NAND element, a trigger, the inverse output of which is connected to the first input of the second NAND element, the output of which is connected to the first output bus that, in order to extend the functionality by making it possible to divide the input pulse sequence into two sequences, the clock is connected to the counter input of the counter, the setup input of which connected to the second input of the first NAND element and the forward trigger output, the first output to the second output bus, and the second output to the R input of the trigger, the C input of which is connected to the output of the second AND NAND element, the second input of which is connected with the first input of the first element NAND, the output of which is connected to the third output.