SU1707751A1 - Device for separating and subtracting pulses from a pulse sequence - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and remote control devices for extracting and subtracting pulses and pulse bursts from a sequence. The aim of the invention is to expand the field of application while simplifying the device. The device contains a pulse counter 1, the first 2 and second 3 code comparison elements, synchronous D-trigger A, decoder 5, AND-HE element 6, reset input buses 7 and pulse sequence 8, tires 9 and 10, set codes, and output tires 11 - 15. In the first mode of operation of the device, any pulse is selected and subtracted from the sequence, the code of which is predefined using code input buses 9 and 10. At the same time, an input sequence pulse is formed on the output bus 15 of the device on tires 9 and 1 0, and at the output 11, an input pulse sequence minus the specified specified SP

Description

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momentum. In the second mode of operation, the device extracts and subtracts a burst of pulses from the pulse sequence. On the input code buses 9 and 10, codes are set that determine the beginning and end, respectively, of the bundle to be extracted. At the same time on the weekend

The bus 11 is formed with an input pulse sequence in which there are no pulses of a given pack, and on the output bus 12 there is a given pack of pulses without the first and last pulses, which are formed respectively on the output buses 13 and 14. 3 Il.

The invention relates to a pulse technique and can be used in automation and telemechanic devices for isolating and subtracting pulses and bursts of pulses from a sequence of pulses.

The aim of the invention is to expand the field of application while at the same time simplifying the device by separating the first and last pulses of the selected packet of pulses, the rest

1 mp pulses of the extracted burst, a sequence of input pulses with the exception of pulses of the burnt burst, as well as a burst of a single pulse.

Figure 1 shows the functional diagram of the device; Fig. 2 shows timing diagrams of the operation of the device in the mode of extracting a single pulse from the input sequence; on fig.Z - the same. in the burst selection mode.

A device for isolating and subtracting pulses from a sequence of pulses comprises a pulse counter 1, the first

2 and second 3 code comparison elements, synchronous D-flip-flop 4. decoder 5. epement AND-NOT b input buses 7 and 8, respectively, reset and pulse sequence, tires 9 and 10, assignment of codes, and also output buses 11 - 15. And The single outputs of the pulse counter 1 are connected to the respective combined inputs from the first groups of inputs of the first 2 and second 3 examples of code comparison, the second groups of inputs of which are combined respectively with buses 9 and 10 of the task codes. The output of the first code comparison element 2 is combined with the zeroing input of the synchronous D-flip-flop 4 and the third information input of the decoder 5, the first information input of which is combined with the direct output of the flip-flop 4 connected by the control input with the output of the second code comparison element 3 and the second information input decoder 5. The strobe input of the decoder 5 is connected to the input bus P. of the pulse sequence, and its city, the fifth output

combined with the corresponding output buses 11-15 of the device and the corresponding inputs of the element AND-NOT 6 connected by the output to the clock input

pulse counter 1, the zeroing input of which is connected to the reset input bus 7, and the clock input of the synchronous D-flip-flop 4 is combined with the third output bus 13 of the device.

The device has two modes of operation. In the first mode, the selection and subtraction of any pulse, the code of which is preset, is provided, and in the second mode, a burst of pulses, with the beginning and coke

bursts of pulses are assigned by the corresponding codes of the number of pulses.

The device works as follows.

After powering up the bus 7

a reset is given a positive signal (Fig. 2a. Za), which sets the counter 1 to the zero state. The trigger 4 is also set to the zero state either by this signal ({the circuit is not shown) or by setting the zero code pulses on the first input bus 9. At the same time, at the output of the first comparison element 2, there is a high potential, which sets the trigger 4 to its initial state.

Suppose that, for example, a third pulse is deducted from a sequence of pulses arriving at the bus 8 clock pulses. To do this, the first 9 and second 10 input code buses are supplied

two codes of the previous pulse number

Ni N2 2 (0010).

The pulses from the bus 8 clock pulses (Fig.26) arrive at the gate input

decoder 5, on the information inputs of which there is a low potential, respectively, from the output of trigger 4 and from the outputs of elements 2 and 3 of the comparison codes (000). Consequently, the pulses from the gate input pass to the first output of the decoder 5. to the first output bus 11 (Fig. 2e) and to the first input of the AND-NOT element b. Positive pulses from the output of the NANDI element 6 are fed to the counting input of the pulse counter 1, the state of the outputs of which vary along the falling edge of the input pulses. On the falling edge of the second pulse, at the outputs of counter 1, a code is generated that matches the code supplied to the input code buses 9 and 10 (0010). those. The codes arriving at the first and second groups of inputs of elements 2 and 3 of the code comparisons coincide and a high potential is formed at the output of the latter (Figures 2c, d). At the same time, the code 011 is set at the information inputs of the decoder 5 and, therefore, the third impulse gc of the bus 8 input impulses passes to the fifth output of the decoder, the fifth; output bus 15 and to the corresponding input element AND-NOT 6.

On the trailing edge of the (third) pulse from the output of the element IS-NOT 6 to the counting input of the counter 1 pulses, the sequence changes the state of its outputs. At the outputs of counter 1, a code is set whose value is greater than the code set on the first 9 and second JO input code buses. As a result, the outputs of elements 2 and 3 of the code comparison again have a low potential (FIG. 2 V. d) and all subsequent pulses again pass. t on the output bus 11 (Fig, 2 e).

Thus, if equal pulse number codes are set on the input buses 9 and 10 of the pulse code, a pulse sequence without a single pulse is formed on the first output bus 11, the number code of which corresponds to (N - 1) which is formed on the fifth output bus 15.

If the first input bus 9 code to submit a binary code, for example, NI 5 (0101), and the second input bus 10 code - a binary code. for example, N2 1 (0001). then a packet of pulses is subtracted from a sequence of pulses, the beginning and end of which are given by the corresponding codes.

In this case, the first pulse from the bus 8 of the input pulses passes to the output bus 11 (FIG. 3 b, e). At the rear, the front of this pulse, at the output of the pulse counter 1, a code 0001 is set, which coincides with code 2. installed on the input bus 10 of the code, therefore, a high potential is formed at the output of the code comparison element 3 (FIG. 3c). When a second pulse arrives from the bus 8 input pulses to the gate input of the decoder 5 at the information, inputs, the last form code 010 and this pulse passes to the third output of the decoder, the third output bus 13, the clock input of the trigger 4 and the third input of the element

AND-NOT 6 (Fig. 3 g) On the back of the Phonot of the pulse received at the clock input of the trigger 4, the latter is set to the B unit state, as well as its D-in ode

there is a high potential from the element 3 of the code comparison (Fig. 3d). At the falling edge of the pulses from the output of the element IS-NE 6, a counter is set at the outputs of the counter 1, which exceeds the value

0 of the installed code, while the codes on the first and second inputs of element 3 of the comparison do not match and the LOW potential is formed at its output. At the information inputs of the decoder 5, a code 100 is generated.

5 and subsequent pulses pass to the second output of the decoder 5, the second output bus 12 and the second input of the AND-HE element 6 (Fig. 3 h).

On the trailing edge of the nth pulse on

The 0 outputs of the pulse counter 1 are set to code 0101 and a high potential is generated at the output of the code comparison element 2 (FIG. 3 d), which returns the trigger 4 to the initial state. At the same time, the code 001 is set at the information inputs of the decoder 5 and the next, sixth pulse passes to the fourth output of the decoder 5, the fourth output bus 13 and the fourth input of the element AND NOT HE

0 (FIG. 3 and). On the rear front of this impedance, at the output of the pulse counter 1, a code is set greater than the value of the set code, and the lowest potential is formed at the output of the comparison element 2. and the code 000 is set up at the information inputs of the decoder 5 and all other pulses of the pulse sequence pass to the first output bus 11 (FIG. 3e).

Thus, if different pulse number codes are defined on the input code buses 9 and 10, which determine the end of the packet, the pulse output sequence is removed from the first output bus 11, and the third 13 and fourth 14 output tires are missing from the third output bus 11 the first and last pulses of a given burst of pulses are removed, respectively, and the remaining pulses of a zero burst of this burst are removed from the second output bus 12.

A device for extracting and subtracting 5 pulses from a sequence of pulses, containing the first and second elements of the comparison, the first groups of inputs of which are connected respectively to the first and second input code buses, a pulse counter, the fault input of which is connected to the reset bus, and the bit outputs are combined with the corresponding inputs of the second group of inputs of the first comparison element, the synchronous D-flip-flop, the input bus, the decoder, and the NAND element, different in that. that, in order to expand the field of application while simplifying the device, the inverse outputs of the decoder are connected to the corresponding output buses and, through the AND-NES element, to the clock input of the pulse counter connected by bit outputs

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Claims (1)

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