SU1377859A1 - Signature analyzer - Google Patents

Abstract

The invention relates to computing and can be used in the test equipment of digital objects. The aim of the invention is to expand the class of controlled objects. The signature analyzer contains the corpse of 1 information inputs, the control inputs Start and Stop 2.3, syncro 4, group 5 information. f outputs, adder 6 modulo two, shift register 7, trigger 8, first element 9, pulse generator 10, first group 11 elements AND, second element 12, first delay element 13, switch 14, register 15, second group 16 elements AND, the element OR 17 and the second element 18 delay. The adder 6 modulo two and the shift register 7 together form the driver 19 of the signatures. In the proposed signature analyzer, it is possible to set an arbitrary number of information outputs of the control object (within the number of information inputs of the analyzer), and the set of controlled outputs of the control object can be specified in any combination, while selectively connecting the outputs of the control object to the analyzer inputs. 1 il. i (L with N 00 ate CD

Description

The invention relates to computing technology and can be used in test equipment of digital objects.

The aim of the invention is to expand the class of controlled objects.

The drawing shows the functional diagram of the signature analyzer.

The analyzer contains a group of 1 information inputs, inputs 2 and 3 Start and Stop synchronous input 4, a group of 5 information outputs, the sum is. torus 6 modulo two, shift register 7, trigger 8, first element 9, (10 pulse generator, first group 11 elements AND, second element 12, first delay element 13, switch group 14, n-bit register 15, the second group of 16 elements AND, the OR element 17 and the second delay element 18. The adder 6 modulo two and the shift register 7 together form the signature generator 19,

Signature analyzer works as follows.

Before starting work, using the switches of group 14, the output of the first delay element 13 is connected to the single inputs of the bits of register 15 in accordance with the required set of monitored information inputs,

When a single signal analyzer appears at input 2, which determines the beginning of the monitoring interval of the input information sequences, the state is set in the O register of the shift 7 and the register 15, and also set to state 1 trigger 8, allowing the very arrival of pulses from the input 4 of the analyzer through the first ele50

ment 9 and the trigger input to the impulse generator produces a single

the output signal of the element is AND 16 with a minimum number j (), for which the corresponding register bit 15 contains one, and so on.

After forming the single SIG-HaJia at the output of AND 16 with the maximum number for which the corresponding register bit 15 contains one, all bits of this register are reset to the state O. Under the influence of the unit values of the signals from the inverting outputs of the bits of the register 15 to the inputs the second element And 12 at its output is formed

ra 10 pulses

After zeroing, the inverting outputs of register bits 15 are set to 1, under the influence of which a single signal is generated at the output of the second element 12. This signal through the first delay element 13 is fed to the input of group 14, the signal through the switches of the group 14 is fed to the single inputs of the corresponding triggers of register 15 and sets them to state 1, then a zero signal is generated at the output of the second element 12.

55

Signature analyzer prepared for use.

Consider one information control cycle, which is performed on a signal at sync-input 4,

The information inputs 1 of the analyzer receive signals from the outputs of the control object. The synchronization signal of the analyzer from the input 4 through the first element And 9 starts the generator 10 pulses. According to the clock pulses of the generator 10 at the outputs of the elements And 16 of the second group, single signals are sequentially generated as follows. At the output of the first element AND 16 of the second group, a single signal is generated by a clock pulse, provided that the first register bit 15 has a single value. This signal is fed to the second input of the 1st element And 11 of the first group and to the second zero input of the 1st bit of register 15, setting it to the state O,

Let i be the smallest order number of the register register 15, containing one (,.,., П). Then, the inputs of the i-ro element of AND 16 are supplied with the enable signals from the inverse outputs of the bits with the numbers 1,. ,,, (i-1) and from the direct output of the i-ro bit of register 15. On the next clock pulse from the generator 10 at the output of the i-ro element And 16, a single signal is generated, which is fed to the second input ir, o of the element And 11 of the first group, and also performs resetting i-ro times and register 15 at its second zero input. Thus, by the next pulse, the smallest order bit of register bit 15, containing one, is determined without taking into account the -th bit. At the next clock signal 1. This signal stops the pulse generator 10, and also through the first delay element 13 sets the state to 1 bits of register 15 in accordance with the code dialed on the switches of group 14. Delay element 13 delays the signal in order to restore the code in register 15 after stopping generator 10.

According to the signals at the outputs of the elements 16, the information is entered sequentially through the elements 11 and 11 from those inputs 1 of the analyzer to which the single values correspond to the dial code in the switches of group 14. The single code values are determined

pulses, a trigger, two elements And, the first delay element and two groups of n elements And, where n is the number of information inputs of the analyzer, the single and zero inputs of the trigger are respectively the Start and Stop inputs of the analyzer, the output of the trigger is connected to the first input of the first element And, the second input of which is the synchronous input of the analyzer, the output of the first element I is connected to the trigger input of the pulse generator, the group of outputs of the signature generator is a group of information outputs of the analyzer, characterized by then, in order to expand the class of controlled objects, the analyzer further comprises an n-bit

the closure of the switch circuits of the group-JQ register, a group of switches, ELEP 14. The information signals from the outputs of the corresponding elements 11 through the element OR 17 sequentially arrive at the information input of the signature generator 19. The synchronization 25 of the signature generator 19 is carried out by the clock pulses of the generator 10 delayed by the second element 18 of the delay 18. The delay of the clock pulses is performed for the time necessary to form the next result of the summation at modulo two.

In the next monitoring cycle, the controlled information is changed at the inputs 1 of the analyzer and when the sync signal appears at the input 4, the analyzer is repeated.

Finishing work of analyzer on entry 35

Signal status

40

the OR or second delay element, the first inputs of the AND elements of the first group are the information inputs of the analyzer, the outputs of the AND elements of the first group are connected to the inputs of the OR element, the output of which is connected to the information input of the signature generator, the contact switches of the group switches are connected to the corresponding information inputs of the register , the reset input of the signature generator is connected to the first input of the installation in the О register and to the single trigger input, non-inverting bit inputs of the register are connected s, respectively, with the first inputs of the elements of the second group, the output of the pulse generator is connected to the second inputs of the elements of the second group and the input of the second delay element, the inputs from the second to (1-1) th i-ro element of the second group are connected to the inverting outputs ( il) -x register bits (i-2, ..., n), the outputs of elements AND of the second group are connected to the second inputs of the corresponding elements AND of the first group and the second input of the installation in О of the register, the inputs of the second element AND are connected to inverting bits the outputs of the reg-output of the second element And connected to the stop input of the pulse generator and the input of the first delay element, the output of which is connected to the disconnecting contacts of the switches of the group, the output of the second delay element is connected to the synchronous input of the signature generator.

3. In this case, the trigger 8 is set to the state O and thus prohibits the passage of pulses from the blood flow 4 of the analyzer to the output of the element AND 9.

The final signature contains a shift register 7 and is output from analyzer outputs 5 for further comparison with the reference.

Claims (1)

Thus, the proposed signature analyzer allows connection and control of the information outputs of the control object in any combination without their preliminary switching outside the analyzer. Invention Formula Signature analyzer containing signature generator generator 5 n five 0 five  country, the OR or second delay element, the first inputs of the AND elements of the first group are the information inputs of the analyzer, the outputs of the AND elements of the first group are connected to the inputs of the OR element, the output of which is connected to the information input of the signature generator, the contact switches of the group switches are connected to the corresponding information inputs of the register , the reset input of the signature generator is connected to the first input of the installation in the О register and to the single trigger input, non-inverting bit inputs of the register are connected s, respectively, with the first inputs of the elements of the second group, the output of the pulse generator is connected to the second inputs of the elements of the second group and the input of the second delay element, the inputs from the second to (1-1) th i-ro element of the second group are connected to the inverting outputs ( il) -x register bits (i-2, ..., n), the outputs of elements AND of the second group are connected to the second inputs of the corresponding elements AND of the first group and the second input of the installation in О of the register, the inputs of the second element AND are connected to inverting bits the outputs of the reg-output of the second element And connected to the stop input of the pulse generator and the input of the first delay element, the output of which is connected to the disconnecting contacts of the switches of the group, the output of the second delay element is connected to the synchronous input of the signature generator.