SU1520526A1 - Device for checking comparison circuits - Google Patents

Abstract

The invention relates to automation and computing and can be used in the implementation of digital control technology. The purpose of the invention is the expanded areas of application of the device. The device contains the counter 1, the trigger 2, the elements AND 4-6, the elements OR 7, 8, the elements 9, 1, 0 unequalities, indicator 11. The establishment of the operating mode of the device is determined by the signals received at the inputs 13, 14 of the device. The signals from the clock input 12 of the device are fed to the counting input of the counter 1 and provide for enumeration of various codes at the inputs of the first group of the controlled comparison circuit 3. If the monitored comparison circuit 3 is malfunctioning, the indicator 11 is turned on. 1 Il.

Description

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The invention relates to automation and computing and can be used in the implementation of digital control technology.

The aim of the invention is to expand the field of application of the device.

The drawing shows a functional diagram of the device.

The device contains a counter 1, a trigger 2, a controlled comparison circuit 3, elements AND 4-6, elements OR 7 and 8, elements 9 and 10 of unequalities, an indicator 11, a clock input 12 of the device, inputs 13 and 14 of setting the operation mode of the device.

The device for controlling the comparison circuits works as follows.

When controlling the comparison circuit 3, the operation is less, the inputs 13 and 14 of the device operation mode must have zero signals. In this case, the output element And there will be a zero signal.

Before starting the control of the comparison circuit 3, which implements the operation less, the counter 1 and the trigger 2 are set to the zero position (the reset circuits are not shown in the drawing). In this case, at the direct output of flip-flop 2, there will be a zero signal, i.e. on the second group of inputs of the controlled comparison circuit 3 there is a zero number. Consequently, the first and last groups of inputs of the controlled comparison circuit 3 receive zero numbers, after which the output of this comparison circuit 3 should be a zero signal when it is in good condition. In this case, the second input 14 specifies the device's mode of operation to have a zero signal, and therefore, the output of the inequality element 9 should also be a zero signal. At the same time, at the direct output of the trigger 2 and at the first input 13 of the setting of the device operation mode there are zero signals, as a result of which the outputs of the AND 5 and 6 elements and, therefore, the OR 8 element also have zero signals. Thus, zero signals are received at both inputs of the inequality element 10, as a result of which there is also a zero signal at its output and the indicator 11 is turned off.

Then, clock pulses are applied to the clock input 12 of the device.

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In the interval from the beginning of the supply of the first clock pulse to the overflow pulse of binary counter 1, the contents of this counter 1 are greater than the number arriving at the second group of inputs of the controlled comparison circuit 3. In this case, under the good condition of the controlled comparison circuit 3, its output should be zero. signal, as a result of which the output of the inequality element 10 should also be a zero signal, at which the indicator 11 is turned off.

At the moment when in the counter 1 there will be the number 11 1 ... 111, a single signal will appear at the output of the And 4 element. At the same time, at the output of element 5, the zero signal remains, since at the direct output of flip-flop 2 a zero signal remains.

Then the clock pulse arriving at the clock input 12 of the device, sets in the counter 1 a zero number. In this case, the overflow pulse from the output of binary counter 1 sets the trigger 2 to state 1, as a result of which a single signal appears at its direct output, due to which the number 111 ... 11 1 goes to the second group of inputs of the controlled comparison circuit 3. In the case of the first group of inputs of the controlled comparison circuit 3, zero jcJo is received, as a result of which the output of this comparison circuit 3 must be a single signal when it is in good condition and, therefore, there must be a single signal at the output of unequality element 9. At the same time, at the direct output of flip-flop 2 there is a single signal, and at the output of the element AND 4 there is a zero signal, as a result of which the output of the element 5 and, therefore, the element OR 8 will be single signals. Thus, single inputs are received at both inputs of the UNIMNITY 10 element, as a result of which there is a zero signal at its output and the indicator 11 is turned off.

At the moment when in the counter 1 there will be the number 111 ... 111, a single signal appears at the output of the AND 4 element, and a zero signal at the output of the OR B element. At the same time, the first and second groups of inputs of the controlled comparison circuit 3, which implements the operation less, receives the number 111 ... 111, as a result of which a zero signal should appear at its output in its good condition, and therefore, at the output of the unequal element 9 zero signal. Thus, zero signals arrive at both inputs of the inequality element 10, as a result of which there is a zero signal at its output and the indicator 11 is turned off.

Then, the clock pulse arriving at the device input 12 sets a zero number in the counter 1. In this case, the overflow pulse from the output of binary counter 1 sets the trigger 2 to the state O, due to which a zero signal appears at its single output.

In the case of a malfunctioning of the controlled comparison circuit 3, which implements the operation less, signals O and 1 appear at its output, and consequently, at the output of the inequality element, at the times when, at the output of the element OR 8, there are corresponding signals 1 and O. As a result, signals 1 begin to appear at the output of the inequality element 10, which include an indicator 11. The indicator can include a pulse expander on a one-shot or a trigger to turn on the display after the first monitored circuit 3 compares nothing Due to the fact that the contents of binary counter 1 are continuously changing, the verification of the comparison circuit 3 is carried out with different codes.

When controlling the comparison circuit 3, which implements the operation more-equal, the inputs 13 and 14 of the device's mode of operation should be, respectively, zero and single signals. At the same time, the control of the comparison circuit 3, which implements the operation more or less, is the same as control of comparison circuit 3 implementing the operation less. If at the same time the first and second groups of inputs of the controlled comparison circuit 3, which implements the operation is more or equal, the numbers 111 ... 111 or 000 ... O or the contents of the binary are received -. counter 1 is greater than the number arriving at the second group of inputs of the controlled comparison circuit 3, then, in the normal state of this comparison circuit 3, its output should be

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a single signal, as a result of which the output of the unequal element 9 should be a zero signal, since at the input 14 of the device operation mode setting there is a single signal.

If the content of binary counter 1 is less than the number arriving at the second group of inputs of the controlled comparison circuit 3, then in good condition of this comparison circuit 3, there should be a zero signal at its output, as a result, there is a single signal at the output of inequality element 9.

The formation of single and zero signals at the output of the element OR 8 in the control of the comparison circuit 3, which implements the operation is equal to, is the same as in the control of the comparison circuit 3, which implements the operation less. Therefore, in the intact state of the controlled comparison circuit 3, which implements the operation more than 25 is equal to, both inputs of the inequality element 10 will simultaneously receive zero or single signals, as a result of which there is a zero signal at its output and the indicator P is off.

When the monitored comparison circuit 3 fails, realizing the operation is greater than or equal, signals O and 1 appear at its output, and therefore, at the output of element 9. unequalities, the corresponding signals 1 and O appear at the time points when the output signals of the SHSh 8 element have the corresponding signals O and 1. As a result, the outputs of the inequality element 10 begin to appear signals 1, which turn on the indicator 11.

When checking circuit 3 comparison,. , implements the operation Not equal, at the inputs 13 and 14 of the assignment of the operating mode of the device there must be single and zero signals, respectively.

Before the start of control of the comparison circuit 3, which implements the operation Equal, the counter 1 and the trigger 2 are set to the zero position. In this case, at the direct output of flip-flop 2, there will be a zero signal, i.e. on the second group of inputs of the controlled comparison circuit 3, there is a zero number. In addition, the first and second groups of inputs of the controlled comparison circuit 3 receive zero numbers, after 30

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The consequence is that the output of this comparison circuit 3 should be a zero signal when it is in good condition. In this case, the input 14 of the device operation mode setting has a zero signal, and therefore, at the output of the element. 9 inequalities should be a zero signal. Simultaneously at the direct output of trigger 2 and at the output of the element OR 7. there are zero signals, as a result of which the outputs of the And 5 and 6 elements, and therefore, to the OR 8 element, there are also zero signals. Thus, on both inputs of the element 10 is not

zero signals come to equivalence, as a result of which on its output there is also a zero signal and indicator 11 is turned off

Then, clock pulses are applied to the clock input 12 of the device.

B interval from the beginning of the first clock pulse to the overflow pulse of the binary counter t

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as a result, a single signal arises at its direct output, due to which the number of 1 11 ... 111 is input to the second group of inputs of the controlled comparison circuit 3. In this case, the first group of inputs of the controlled comparison circuit 3 receives a zero number, as a result, at the output of this comparison circuit 3 there should be a single signal when it is in good condition, a research institute, and therefore, there should be a single signal at the output of the unequal element 9. Simultaneously, at the inverse output of trigger 2 there is n0

the left signal, so that the output of the element And 6 will be a zero signal. At the same time, at the direct output of flip-flop 2 there is a single signal, and at the output of the element I..4 there is a zero signal, as a result of which the output of the element 5 and, therefore, the element OR 8 will be single signals. Thus, at both inputs

the contents of this counter 1 is not equal to 25 unequality element 10 post

the number arriving at the second group of inputs of the controlled comparison circuit 3. In this case, under the good condition of the controlled comparison circuit 3, there should be a single signal at its output, as a result of which there should also be a single signal at the output of the inequality element 10. At the same time, at the output of the element OR 7, the inverse of the output of the trigger 2 and the input 13, specifying the operation mode of the device, there are single signals, as a result of which the output of the element AND 6 and, consequently, the element OR 8 will be single signals. Thus, single signals arrive at both inputs of the inequality element 10, as a result of which there is a zero signal at its output and the indicator 11 is turned off.

l the moment when in the counter 1 bude the number 111 ... 111, at the output of the element And 4 there will be a single signal. At the same time, at the output of the element 5, the zero signal remains, since at the forward exit of the flip-flop 2 a zero signal remains. However, at the output of the element And 6 remains a single signal.

Then the clock pulse arriving at the clock input 12 of the device, sets in the counter 1 a zero number. In this case, an overflow pulse from the output of binary counter 1 sets trigger 2 to state 1,

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single signals are fallen, as a result of which there is a zero signal at its output and indicator 11 is off.

At the moment when the number 111 .. 111 is in the counter 1, a single signal appears at the output of the AND 4 element, and a zero signal at the output of the OR 8 element. At the same time, the first and second groups of inputs of the controlled comparison circuit 3, which implements the operation is not equal, receives the number 111 ... 111, as a result of which a zero signal should appear at its output in its intact state, and consequently, at the output of the 9 inequality element there should be a zero signal. Thus, on both inputs of the element of unequalities, zero signals arrive, as a result of which there is a zero signal at its output and indicator 11 is turned off.

Then the clock pulse arriving at the input 12 of the device, sets in the counter 1 a zero number. In this case, the overflow pulse from the output of binary counter 1 sets the trigger 2 to the state D, as a result of which a zero signal appears at its single output.

In case of a malfunction of the controlled comparison circuit 3, which implements the operation is not equal, at its output, and consequently, at the output

of element 9, the O and 1 signals appear at the times when the output of the element OR 8 has the corresponding signals 1 and O. As a result, the output of the inequality element 10 begins to appear signals 1, which turn on the indicator 11,

When monitoring the comparison circuit 3, which implements the operation equally, the inputs 13 and 14 of the device operation mode must contain single signals. In this case, the control process of the comparison circuit 3, which implements the operation equally, is the same as the control process of the comparison circuit 3, which implements the operation is not equal. If at the same time the first and second groups of inputs of the controlled comparison circuit 3, which implements the operation is equal, receive the numbers 111 ... 111 or 000 ... 000, then in good condition of the circuit, there should be a single signal at its output, as a result 9 inequalities should be a zero signal, since at the input 14 of the device operation mode setting there is a single signal.

If the content of binary counter 1 is not equal to the number arriving at the second group of inputs of the controlled comparison circuit 3, then in good condition of this comparison circuit 3, there should be a zero signal at its output, as a result of which there is a single signal at the output of inequality element 9.

The formation of single and zero signals at the output of the element OR 8 in the control of the comparison circuit 3, which implements the operation is equal, is performed in the same way as in the control of the comparison circuit 3, which implements the operation is not equal. Therefore, in a good state of the controlled comparison circuit 3 implementing the operation, zero or single signals will simultaneously arrive at both inputs of the inequality element 10, as a result of which there is a zero signal at its output and the indicator 11 is turned off.

In the case of a malfunctioning controlled comparison circuit 3, which implements the operation equally, O and 1 signals appear at its output, and therefore, at the output of the inequality element 9, the corresponding signals 1 and O appear at

the time when the signals O and 1 are output at the output of the B1I B element. As a result, the output of the 10-imbalance element begins to appear signals 1, which turn on the indicator 11.

Such a construction. Devices for controlling comparison circuits allow 0 to control a large number of types of comparison circuits.

Claims (1)

Invention Formula 5 A device for monitoring comparison circuits containing a counter, a trigger, an indicator, two AND elements and a first unequal element, the counter overflow output being connected 0 with a counting trigger input, a group of information outputs of the counter is connected to a group of inputs of the first element And is a group of information outputs of the device for connecting to the first group of information inputs of a controlled comparison circuit, the direct output of the trigger is connected to the direct input of the second element And the information output of the device for connecting to the second group of information inputs of the controlled comparison circuit, the first input of the first element the nonequalitarian value is the information input The device for connection to the output of the controlled comparison circuit, the counting input of the counter is the clock input of the device, the output of the first element I is connected to the inverse input of the second element I, which is characterized by the fact that it is entered the second element of non-equivalence, the third element is AND 5 and two elements OR, and the group of information outputs of the counter is connected to the group of inputs of the first element OR, the output of which is connected to the first input of the third element AND, P the output of which is connected to the first input of the second element OR, the output of which is connected to the first input of the second inequality element, the output of which is connected to the information input of the Indicator, the inverse output of the trigger is connected to the second input of the third element And, the output of the second element And is connected to the second input of the second element OR, exit per5 II152052612 element of the inequality of soy-first element of inequality The dinene with the second input of the second el is the first and the second unequal, respectively, the third is the input of the mode setting. the third element And and the second entrance of the device.