SU444190A1 - Apparatus for calculating ordered selection functions - Google Patents

Description

I

The invention relates to automation and computational technology and can be used in operational devices of automatic control and monitoring systems: A device is known for calculating one of the functions of an orderly selection of a median function containing a majority element, with an OR input circuit, triggers, inverters, And schemes and schemes

Comparison, the known device allows the selection of an average value of an odd number of binary numbers represented by a sequential code. However, the known device is characterized by low speed, due to the sequential nature of processing bits of the original numbers.

The purpose of the invention is to increase the speed of calculating any Kth number from an 11bit binary number.

; For this, the proposed device contains delay elements, bit selection circuits and registers, whose outputs of the same name are associated with the first (informational inputs of the corresponding

comparison circuits and with the corresponding inputs of the bit selection circuit, the output of each; to the bottom of which is connected to the corresponding second information inputs of the respective comparison circuits, the output of the equivalence of the comparison circuit of each previous bit through the delay element is connected with the control input of the comparison circuit of the subsequent bit, and the zero and single outputs of these circuits through the corresponding circuits OR the corresponding register is connected to the zero and one states, respectively, with j control-5 inputs of the high-order comparison circuits connected to the corresponding m control inputs of the device.

The drawing shows the functional diagram of the device.

The proposed device contains numeric registers 1, outputs of the same name

The bits of which are connected :: by the first informational inputs of the comparison circuits 2 and with the inputs of the discharge circuits of coastal 3;

OR circuits; 4 settings of the h c) new regs of the OCTpOB in the zero state and schemes OR 5 of the settings of the number of: registers in a single state, which are associated with the zero and single outputs of the comparison circuits, respectively; control buses 6 connected to the control inputs of the high bit comparison circuits, and delay elements 7 that are turned on; between the output of the equivalence of the comparison circuit of the previous bit and the control input of the comparison circuit of the subsequent bit.

The outputs of the bit selection circuits 3 are connected to the second information inputs of the same name comparison circuits 2.

The device works as follows. The numbers to be processed are entered into the numeric registers 1. The values of the same-digit bits of all the numeric registers go to the inputs of the corresponding bit selection circuit 3, If the number of units entering the inputs of the selection circuit exceeds its threshold Q, a single value is generated at its output. Otherwise, the signal at the output of the bit selection circuit takes a zero value.

To operate the device, it is necessary to simultaneously send control signals to all control buses 6. According to these signals, the comparison schemes of the two most significant bits work. A signal appears at one of the three outputs of each of the comparison circuits 2; at the output Q, if at the output of the high bit of the numeric register 1 there is a zero value, and at the output of the selection chip 3 - a single value, at the single output b - in the opposite situation, at the output of equivalence - if the values are equal.

The signal at the zero output of the comparison circuit 2, through the circuit OR 4, sets all bits of the same numeric register 1 to the zero state. From the UNIQUE output of the comparison circuit, the 2 signal through the circuit OR S sets all bits of the corresponding numeric register to the one state.

A change in the state of numerical registers, the values of the higher bits of which differ from the values of the signals at the output of the selection circuit 3 of this bit, leads to a change in the values of the signals applied to the inputs of the gating circuits of selection 3. As a result, the values of the signals at the outputs may change selection schemes 3 subsequent bits.

Those numeric registers whose leading bits are equal to the value of the sirnal at the output of the bit circuit in | 3 will generate signals at the output of the equivalence of the comparison circuit 2. They are delayed by delay elements 7 for the time required to change the state of bits the devices are based on the results of comparing the higher bit rates, and lead to the triggering of the comparison circuits 2. the subsequent second bit.

, In the second bit, the values of bits, the considered numeric registers will be compared with the corrected value of the signal at the output of the second bit selection circuit. The operation of the launching second-bit comparison circuits is analogous to that considered for the higher bit. Only for those numeric registers in which the value of the second bit coincides with the steady-state value of the signal at the output of the bit selection circuit, the comparison circuits of the subsequent third bit will start.

The described actions will be performed m times by the number of digits of the processed numbers. As a result of this, the outputs of the bit selection schemes will set the binary

the number corresponding to the K-th largest value of the number of processed numbers, where

K p-9-c.

(one)

If from n binary numbers it is required to choose the K-th number by value, then the threshold of 40 bit selection schemes in accordance with (1) should be chosen equal to

(2)

PRI m e jg. Four numbers are given:, B) 110,,. From the indicated set of numbers, it is necessary to select the second number by value.

city:

In accordance with equation (2), over, the horn of bit 3 selection circuits should be taken equal to 9 3 (selection 3 of 4). Only in the presence of at least three -units at its inputs at the output, according to a single signal. An example is shown in table. From the table it can be seen that as a result of the operation of the device, at the output of the bit selection schemes, the number of IT is determined, which is the second largest among the numbers under consideration. Thus, the device allows 25 to increase the speed of calculating the function of an ordered selection from an arbitrary set of binary numbers. Subject of the invention. A device for calculating an ordered selection function, comprising comparison circuits 36 and OR circuits, characterized in that, in order to increase the speed of calculating any Kth number from an arbitrary set of binary numbers, the device contains delay elements. and the registers whose outputs of the same-named bits are associated with the first information inputs of the respective comparison circuits and with the corresponding inputs of the bit selection circuit, the output of each of which is connected to the corresponding second the information inputs of the corresponding comparison circuits, while the output of the equivalence of the comparison circuit of each previous discharge through the delay element is connected with the control input of the next release circuit, and the zero and single outputs of these circuits are connected via the corresponding OR circuits respectively setting the corresponding register to zero and one states; moreover, the control inputs of the high-order comparison circuits are connected to the corresponding control inputs of the device.