SU637810A1 - Mn-digit number sorting arrangement - Google Patents

Description

(54) DEVICE FOR SORTING M U-DISCHARGE

NUMBERS

Thanks to the indicated. 1 constructive way, the speed is improved, since for the ordered sorting of these Numbers, it is required (4-1).

This allows a significant (2-4 order of magnitude) increase in the speed of the device for sorting n and bit numbers.

Functional diagram of the device shown in the drawing.

The device contains m registers 1, S which record the original numbers. la, and result register 2, in which the next maximum (minimum) number is formed. The single and zero outputs of registers 1 and 2 are connected to the information inputs of comparison circuits 3, the control inputs of which are connected to the input bus 4 via the first elements 5, the first and second inequality outputs of circuits 3, due to the position of the switch 6, are associated with the corresponding inputs of the element OR 7, the output of which is connected to the installation of the zero state of the trigger 8, the equality outputs of the comparison circuits 3 are connected to the control input of the corresponding prohibition nodes 9, the second and third inputs of which are connected respectively to control buses 10 and 11c. The outputs of nodes 9 are connected to the second inputs of the corresponding elements AND 5. The installation input into a single state of the trigger 8 is connected to the clock signal bus 12, and its forward and inverse outputs are connected via switch 6 to the first input of the second And 13, the second input of which is connected to the control bar 14. The output of the element I 13 is connected to the input of setting the result register 2 to the zero state. At one time control of the result register 2 is connected to the corresponding outputs of the switch 15, the input to torogo associated with shknoy clocks signals 12 s, setting inputs bit result register rows in single sostonie 2 connected to control bus 16.

The device works as follows.

At the beginning of operation, the switch ne ne revolts to the position corresponding to the sorting of numbers in order of their decreasing or increasing (the delay of switch 6 in the drawing corresponds to the sorting of numbers in order of their decreasing). The register 1 registers the initial numbers, and the result register 2 and KONtMyTaTop 15 are reset to their initial state (the circuits for entering information into registers 1 and setting the register 2 and the switch 15 to the zero are not shown in the drawing). Pa. The bus 11 is given a signal that sets all the nodes of the prohibition 9 in such a position that the elements of AND 5 are open. After this the device is ready for operation.

The first clock signal is now supplied to the bus 12, which translates the encoder 15 to the first position. In this case, the first (senior) register of the result register 2, in addition, trigger 8, is prepared for operation (at the first input of the bit control).

1 and prepared in

element 13 and to work. Then, a signal is fed to the tin 16, which enters the first (most senior) bit of the result register 2 units (along the circuit prepared by the first output of the switch 15). After that, the bus 4 is supplied with a signal that passes through the open elements AND 5 to the control inputs of all comparison circuits 3 (any known ones for comparing two n-digits having inequality outputs, 4 and equality output can be used as them) The comparison schemes 3 compare the numbers (N1) in the registers 1 belonging to them with the number in the result register 2 (100,., 0). As a result of this comparison, the signal at the output of the inequality is greater than or equal to, any comparison circuit 3 is equivalent if the number in the corresponding register iMJSlOO. ,, 0 (signals that appear at the outputs of the equality of the circuits 3 do not acting on the prohibition nodes 9, since the signal on the control bus 10 is not supplied),

Thus, if at least B one of the registers 1 finds the number K; i Я00, .. 0, then the signal is given at the output of the corresponding comparison circuit. 3 will pass through switch b, the element OR 7 and will go to the input of the installation in the zero state of the trigger 8. The trigger 8 will set to zero and feed the input element I 13 to inhibit both c and d and al.

After the termination of the signal on bus 4, a signal is sent to bus 14, since AND element 13 is closed, this signal will not go further to the device, and result register 2 will remain recorded in high order. So, by the end of the first cycle of operation, the result of register 2 will be recorded in the first discharge if at least one of the registers 1 finds a number greater than or equal to iOO .., 0.

Claims (2)

If in all registers 1 there are numbers less than 5e than 100 ... O, then the inequality outputs will be greater than or equal to the comparison circuit of 3 signals, therefore, trigger 8 will remain in position. Then the signal from the bus 14 passes through the open element and 13 to the inputs of setting the result register 2 to the zero state. The first bit of the result register 2 returns to the O position through the prepared circuit (at the first input of the bit control). Thus, if all registers 1 will have numbers smaller than 100 ... O, then by the end of the first one, the same work in the first (senior) discharge register of result 2 will be written O. A second clock signal is then supplied to bus 12, and the operation of the device is repeated. By the end of the second cycle of operation, the second register de register 2 will be recorded if at least one of the registers 1 finds a number greater than or equal to the number formed in the result register 2 for two operation cycles. Otherwise, the result will be recorded in the second discharge register. After the termination of p clocks in the register of result 2, a number equal to the maximum value of the number stored in one of the registers 1 will be formed. In (n + 1) clock cycle the switch 15 is transferred by bus 12 to the (rt + l) position in order not to change the contents of register 2. The bus 10 goes to the bus 10, the prohibitory nodes 9 go to work, the signals from the other buses (4,14,16) are received in the same way as in the previous cycles. The signal on bus 16 will not cause any changes in the result register 2, since switch 15 is transferred to the (t7 + l position). The signal on bus 4 will pass to the control inputs of all comparison circuits 3, but only of the comparison circuit 3, where the register 1 belonging to it contains the maximum number equal to the format in result register 2. The output from the equality output of the corresponding comparison circuit 3 goes to the control input of the prohibition node 9 belonging to this comparison circuit 3. The prohibition node 9 translates intothe closed state and the AND 5 element are closed at the second input. Thus, in the future, the signal from bus 4 will no longer pass to this comparison circuit 3, which means register 1, where the maximum number already found is found, in further work will not be accepted. After that, the result of the result register 2 is selected (maximum number), and it is reset to the initial (zero) state. Then another clock signal is sent to the bar 12, and the device starts searching for the maximum number of the remaining numbers (without chose data). The operation of the device is repeated cyclically until all numbers in registers 1 are sorted in order of decreasing. To sort the numbers in order of increasing, switch 6 is moved to another position. The operation of the device is similar to the previously described one, only now each time the selection of the minimum number from the remaining numbers will be carried out. At the same time, in the next discharge of register 2, it will be saved if in this operation cycle the numbers in all non-excluded registers 1 will be greater than or equal to the number formed in register 2 for the past operation cycles (including this one). In the opposite case, in this register de register 2, the next minimum number will be selected from register 2, on the (n + 1) clock cycle, and the corresponding register 1 will be excluded from further work with the help of prohibition node 9 belonging to this register 1 The device has a high speed, since for sorting the number of rj-digits it is required "1 (r1-i) cycles of operation, while for the known devices it is necessary 2-cycles. Apparatus of the Invention A device for sorting n n-bit numbers containing more than n registers, outputs each of which are connected to the inputs of the comparison circuits, the other inputs of which are connected to the outputs of the result register, the output buses of the comparison circuits are connected via switches from the input element OR, elements AND, the trigger, the inhibit nodes, are different in that, in order to increase the speed, the equality output of each of the comparison circuits is connected to the control input of the corresponding inhibit node, the other inputs of which are connected to the device control buses and the output to one of the inputs of the first element AND, the other input of which is connected to the input bus of the device, and the output to the control input of the comparison circuit, the output of the OR element is connected to the trigger input, the other input of which connects with the uiHHOft clock signals, and the outputs, through a switch, to the input of the second element I, the other input of which is connected to the control bus of the device, and the output to the installation input E of the zero register of the result, the inputs of the bit control of which are connected to the output Coad 1ugatora, whose input is connected to shino.ch clock signals, and inputs a setting state of the single bit result register rows are connected to the bus control device. Sources of information taken into account in the examination: 1. Certificate of authorship of CCC and &; "463968, class Q 06 P 7/00, 1954. 2. Authors certificate of the USSR 263277, kl.SchOb R 7/00, 1956. ;