SU1633529A1 - Device for majority sampling of asynchronous signals - Google Patents

Abstract

The invention relates to automation and computer technology and can be used as a majority device when receiving signals over various communication channels, in redundant devices with a large redundancy factor and in a number of other cases. The aim of the invention is to expand the field of use of the device by implementing the majorization principle M of K. At the output of the device, a potential is formed when not less than M of K signals from the device inputs arrive in the time determined by the delay element. The value of M is changed by writing the corresponding number to the register. 1 il.

Description

The invention relates to automation and computing and is intended to work in redundant devices.

The aim of the invention is to expand the field of use of the device by implementing the majorization principle M of K.

The drawing shows a block diagram of the device.

The device contains a group of input triggers 1, three groups of elements AND 2-4, element AND 5, element OR 6, delay element 7, control trigger 8, register 9, comparison circuit 10 and counter II, as well as request inputs 12, clock input 13 and output 14 of the device.

The device works as follows.

In the initial state, the group of input triggers I, control trigger 8 and counter 11 are set to state O, register 9 is entered in the code of M. The zero state of control trigger 8 generates a potential that opens the elements I 2 and prohibits the passage of clock pulses through the element i five.

The signals arriving at the information inputs J2 set the corresponding triggers 1 to state I, and simultaneously these signals go to the inputs of the element OR 6. The first impulse received at information input 12 delayed by the delay element 7 for the time during which the asynchronous signals are collected on the single input trigger 8 control. The latter, with a transition to state I, generates a potential that closes the AND 2 element and permits the passage of clock pulses through the AND 5 element to the second

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ry inputs of the elements And 3 and 4 of the first channel. In this case, the trigger of the first channel can be either in the zero or in the single state. If the trigger of the first channel is in the zero state, the clock pulse through the open element And 3 is fed to the input of the element And the second channel. If the trigger of the first channel is in the single state, the clock pulse (passes through the open element AND A to the single input of the first trigger, transferring it to the back edge state O).

Thus, to set K triggers to the zero state, K clock pulses are necessary, and K pulses will also be sent to the input of counter 11.

If the number of summable units — K — in counter 11 is not less than the code written to register 9, the output potential of the comparison circuit 10 is set to the resolving potential, otherwise there is no permitting potential at the output of the comparison circuit 10.

The installation of the counter 11 in the initial state is carried out by applying a pulse to the installation inputs from the output of the element OR 6 (the installation circuit of the meters 1I to the state O is not shown).

Claims (1)

Invention Formula A device for the majority selection of asynchronous signals, containing a delay element, an OR element, an AND element, and a processing channel, each of which contains an input the trigger and the first element AND, the first input of which is connected to the corresponding information input of the device, and the output of the first element AND of each channel to the corresponding input of the OR element, the output of which is connected to the input of the delay element, characterized in that majorizing M from K, the register of the counter, the comparison circuit and the control trigger are entered into the device, and the second and third elements I are entered into each of the processing channels, the first inputs of which are connected to the inverse and right at the output of the input trigger of its processing channel, and the second inputs - with the output of the second element And the previous processing channel, the outputs of the first and third elements And each processing channel are connected to the S and R inputs of the input trigger of their processing channel, the clock input of the device is connected to the first input of the device element AND, the second input of which is connected to the direct output of the control trigger, and the output to the input +1 counter. ka and second inputs of the second and third elements And the first processing channel S and R inputs., control trigger connected to the outputs of the delay element and the second element And the last processing channel, respectively, the inverse output of the control trigger is connected to the second inputs of the first elements And all processing channels, the first and second information group inputs of the comparison circuit are connected to the outputs of the register and the counter, and the output of the comparison circuit is the output of the device.