SU962900A1 - Device for interfacing subscriber's post with digital computer - Google Patents

Description

groups, the counter input is connected to the clock output of the digital computer, and the output is connected to the first input of the terminal number register and the first decoder input, ie the outputs of the first and second decoders (i 1, M) are connected respectively to the second and third control inputs of the ix group terminals , the output of the register of the terminal number is connected to the input of the second decoder, and the second input with the control output of the digital computer zero input of the trigger of the availability of requests and the control input of the buffer register the i-th input of the j-ro element OR (j 1, K) of the first group of the priority block is connected to the output of the request of the i-ro terminal of the j-th group, a shift ring register, a group of counters of the number for, groups of comparison circuits, K groups of I-elements, output a switch, an And element, a counting counter, a register of a wake, a control trigger and a pulse generator, the outputs of the OR elements of the first group are connected to the corresponding inputs of the register, the output of which is connected to the control input of the output switch, the jth information input from It is connected with polling inputs of the j-th group terminals, the first input of the t-ro element and the j-th group is connected to the request output of the 1st terminal of the j-th group, the second input to the i-th output of the shift ring register, and the output to The 1st input, jr of the OR element of the second group, the output of which is connected to the first input of the jth group comparison circuit via the j-th number counter, the second input of which is connected to the output of the counter-reading counter, and the output to the jth the information input of the switch, the control output of which is connected to the first inverse input of the AND element and zero a control trigger input connected by a zero output to the second inverse input of the element I, and a single input to the start output of a digital computer and an installation input of a detracting counter whose count input is connected to the output of the element I connected by a direct input to the first output of the pulse generator, the second input of which is connected to the input of the shift ring register. FIG. 1 is a block diagram of the device; in fig. 2 is a priority block diagram. The device (Fig. 1) contains gpyp py 1 terminal 2, the buffer register decoders 4 and 5, counter 6, regis 7 terminal number, the element OR 8, the trigger 9 availability request, a digital computer (DVR) 10, block 11 priority (FIG 2) including the elements of OR 12 and 13 of the first and second groups, register 14 of wok, shift ring register 15, subtractive counter 16, pulse generator 17, counters of 18 number of application quota, comparison circuit 19, group, output switch 1mutator, consisting of AND 20 group elements and an OR 21 element, control trigger 22, AND 23 element and K groups of elements ntov 24 and also outputs 25 .oboznacheny request and polling input terminals 26 2, control input 27 and data inputs 28 and outputs 29, priority unit 11. The device is working. after; in this way. The operation of the device is considered in an example of its use for the classes of programmed training. Each group 1 of terminals 2 is a programmable learning class, and each terminal is a student console. In response to the teacher's question, the students each at their own terminal 2, by pressing the corresponding button, form one of the response options. The CVM 10 reads the answers from all terminals in 2 of the same class, issuing a reading signal and after processing the processing end signal. Students of each class generally work independently with their teachers and therefore service request signals accompanying answers can be generated from several terminals in several classes. Single request signals from the outputs of 25 terminals 2 through the corresponding element OR 12 enter the corresponding bits of register 14, single signals at the outputs of the bits of which indicate the presence of service requests from the corresponding terminals 2. At the same time: the request signals arrive at the corresponding AND 24 elements. The pulse generator 17 generates a series of pulses corresponding to the number of terminals 2 in the group, which is fed to the input of the annular shift register 15. In the first bit of this register is stored one The signals, which under the action of the control signals from the generator 17, will sequentially pass through all bits of the ring shift register 15. At the same time, the corresponding elements AND 24 are simultaneously viewed, extracting the request signals from the terms 2 of all groups arriving at the inputs of the AND 24 elements. Signals requests from ka) hdai terminal group 2 successively arrive through the element OR 13 to the counting input of the counter 18. Thus, the counting

requests from each class of 1 terms of 2.

The digital computer 10, after completing the service of the previous cycle, sends an initial start signal, which sets subtractive counter 16 to one state. The same signal, arriving at the unit input of the trigger 22, sets it to the unit. Zero signal with. zero output of the trigger 22 is fed to the second inverse input element And 23 and prepares its opening. Since the subtractive counter 16 is in the single state, and the counters 18 contain the number of requests codes, then at the outputs of the comparison circuits 19, zero signals will be generated, which through the AND 20 elements and the OR 21 element arrive at the first inverse input of the AND 23 element and thereby permitting the arrival of signals from the output of the generator 17 to the counting input of the subtractive counter 16 As a result of this, codes of successively decreasing numbers are sequentially formed in the subtractive counter 16 When the code of the subtracting counter 16, with the code of the number of requests, in some counter 18, at the output of the corresponding comparison circuit 19, a single signal is generated, which through the element and 20, opened with a single signal of the corresponding register bit 14, is fed to the inputs 26 of the terminal 2 of the corresponding group, in which the largest the number of service requests. Through the element OR 21, this signal is fed to the zero input of the trigger 22, setting it to the zero state, and to the first. Inverse input of the AND 23 element, closing the eroj and thereby stopping the flow of signals from the second output of the generator 17 to the subtracting counter 16. After the end the services of the corresponding terminal group 2 remove the request signals and set the corresponding register bits to the zero state.

The digital computer 10 again generates a control signal for the start from output 13, initiating a new service cycle. To change the service discipline, it suffices to remove the connection between the control input 28 of the priority block and the installation input of the counter 16. In this case, the launch trigger from the digital computer 10 will install only the control trigger 22 into the unit. On the subtractive counter 16, the codes will start to form not from the maximum, but from the previous value, providing the service with lower priorities.

Thus, the device provides first-class service to the class in which the largest number of terminals are awaiting service.

which increases the bandwidth of the device.

Claims (2)

1. Author's certificate of the USSR 736085, cl. C 06 F 3/04, 1978. 2. USSR author's certificate on application 272: 4075 / 18-24, cl. G 06 F 3/04, 1979 (prototype). F td