SU1418740A1 - Device for simulating mass service systems - Google Patents

Abstract

The invention relates to computing and can be used to simulate processes in QSS queuing systems. The purpose of the invention is to expand the field of application of the device by simulating a QS with cyclic group dispatching discipline. To achieve this goal, the device comprises a polling control unit including a ring shift register and a decoder. The device allows you to simulate the operation of closed QS with a finite number of homogeneous sources having buffer memories and serviced with cyclic group dispatching discipline. 5 il.

Description

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The invention relates to computing technology and can be used: for modeling processes in queuing systems (QS),

The purpose of the invention is to expand the functionality of the device by simulating a QS with a cyclic group dispatch discipline.

; FIG. 1 shows a structural ckeMa device; FIG. 2 is a scheme for shifting; in fig. 3 is a diagram of the form of the resolver I signals of resolution; in fig. 4 is a diagram of the polling unit; in fig. 5 is a diagram of a polling control unit.

The device (FIG. 1) contains M homogeneous sources 1 of the application, consisting of element 2, second element I 3, block 4 of the shift, generator 5 impulses of the order, third element AND 6, element OR NOT 7, p dummy counter 8 pulses, the first element And 9, the trigger 10 And; counter 11 pulses. In addition, the device contains a shaper 12 service enable signals, the fifth element OR 13, the first element SH 14, the element AND 15, the third element OR 16, the M groups of elements AND 17, the fourth OR element 18, the polling block 19, the block 20 random time delay block polling control 21, the second element OR 22 and the generator 23 clock pulses.

Block 4 shift (Fig. 2) consists of nodes 24-26. Node 24 is a standard bidirectional shift register with a serial (if logical O is supported at input V, and logical 1 is connected with V) and parallel (with logical 1 at V and V) recording information. Node 25 is designed to determine the priority bit of a standard shift register for service according to the principle of first come — first served. Priority is considered the first highest bit in which there is 1.

Node 26 performs the function of blanking a logical 1 in the priority bit of the de-shift register without changing the state of the remaining bits. This node and a typryt exclude applications that enter service from the source queue.

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The bit - the register should be chosen from the average cycle time of the service of one source, i.e. from the time between the previous queuing of the source of the request, such a condition is necessary so that applications belonging to the source are not lost from the queue as a result of successive shifts in the register.

Node 25 contains an OR element 27, a prohibition element 28, an OR element 29 and a delay element 30 that provides a synchronous receipt of a polling signal to the information input of the prohibition element 28 with a signal coming from the output of the OR element 27 to the control input of the prohibition element 28, the output of which is the output of the no-order signal in the queue of the shift block 4.

The output of the first bit of the node 24 is output by the presence of the queue of the shift block 4.

Input V of node 24 is the input of resolving the parallel input of information. The components of the shift block also include elements AND 31, n elements OR 32, elements NOT 33 and elements 34 of delay.

Shaper 12 of the service enable signals (Fig. 3) contains triggers 35, elements AND 36, differentiating elements 37, pulse expanders 38, and element OR 39.

Block 19 of the survey (Fig. 4) is designed to perform a survey of state 0

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The SRI of the bits of the standard shift register of block 4 in each source of the application. The polling unit 19 comprises a trigger 40, a delay element 41, an OR element 42, and a group of delay elements 43.

The polling control unit 21 (Fig. 5) consists of an annular shift register 44 and a decoder 45. The register 44 is designed to generate a binary code with which the cyclic polling unit 4 of the shift in each source is queried. The decoder 45 is designed to form an alternating logical 1 with the outputs M of the polling control unit 21.

Counter 11 is a standard binary counter. It is intended for counting the quotes, received: their

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from each source to the system (to the queue and to the service), in order to simulate, together with the AND-NOT element, 2 states of the buffer memory of this source, i.e. it contains information about the number of occupied cells in this buffer memory. The counter size is determined by a binary number equal to the capacity of the source buffer memory. Since it is equal to three in the device (binary number 11), then the counter size 11 is two. The first and second outputs of the counter are respectively the outputs from the younger and older bits. If the contents of counter 11 are less than three, therefore, there are free cells in the buffer memory of the source, and generator 5 can download applications to the system with a certain frequency. If the content is three, then, respectively, the source buffer memory is full and elements 2 AND-NOT and AND 9 prohibit the operation of generator 5.

The reversible counter 8 is designed to simulate the states of the buffer zone of the source (queue) in the central computer, i.e. this counter contains information on the number of queued requests and servicing. Counter width is also chosen equal to two.

The device works as follows

From the output of the generator 5 impulses to the information input of the 4th shift unit, through element I 9, impulses arrive that simulate the input flow of the application from the first source. Similarly, this happens in other sources. According to the positive clock pulse difference from generator 23 arriving at the synchronization input of the shift unit 4, the sequential information input is shifted to the right, since at the initial moment of operation of the devices at the start input there is a logical O. In the counters 11 and 8, Post-tucked into the system applications. If their number in the counter 1 is equal to the capacity of the buffer memory of the source, i.e. three, the element AND-NOT 2 and the element And 9 prohibit entry of a wok into the system (in block 4 of the shift). This simulates the emergency situation.

Atsi is just a source when its buffer memory is full.

At the same time, a signal is sent to the trigger input about the service resolution (hereafter the signal about the end of service of the application and the resolution of service following the queue number). This signal by

the arrival of a clock pulse passes the shaper 12 of the service resolution signals (Fig. 3), resets the trigger 10 at all sources of demand, and starts the polling unit. In the same

the time from the setup input to the polling control unit 21 is received the setup signal.

From polling block 19, a certain delay is output (FIG. 4).

logical 1 to the input of the resolution of the parallel information input of the 4th shift unit (triggers the trigger 40) and to the first inputs of the I17 elements. In the block 21, upon the arrival of the installation

of its signal, the register 44 is reset to its initial state, as a result of which a binary code 000 ... 01 is generated at the outputs of the 1-M decoder, which enters the second inputs of the And 17 elements. Thus, the polling signals from the information outputs 1-8 of the 19th pass t through the elements of the first group 17, and the elements of the other groups at the outputs have a logical level of O.

When polling signals arrive at the inputs of the shift unit 4 (Fig. 2), the contents of register 24 are read into nodes 25 and 26, as a result of which the service is selected the most

priority application (logical 1 is applied to the corresponding input element OR 13 and to the first input of the trigger 10) and is excluded from the queue (node 26 performs blanking

1 in the priority bit and enters the information in the parallel code through the inputs D, - Dj into the register, since 1 is supported at the input V. In all other blocks 4 of the shift, the information in the registers does not change and the corresponding inputs of the element OR 13 and the trigger 10 are supplied to O. Thus, the service through the element OR 13 comes in

ka from the first source. In the absence of a bill in the interrogated block 4 of the shift, at the output of the prohibition element 28 a logical

1, which, via the WLR 16, enters the service enable signal 12 into the driver 12. This signal on the arrival of the clock pulse restarts the polling block 19, as well as through the OR element 22 - the polling control block 21. As a result, the code 0000 ... 10 is generated at the output of block 21, i.e. The second source queue is already polled.

At the end of the service of the application from block 20, a signal is received to allow the scientific research institute of the next service. This signal, as well as the initial launch of the signals, comes through the OR 18 B element of the driver 12, as well as to all sources of the input. It passes through the AND 3 element only in the first source (the trigger 10 supports output 1) and the subtraction mode is performed in the reversible counter 8.

Further, the device may experience two possible situations.

If the reversible counter 8 after completing the subtraction mode contains applications, the element OR NOT 7 outputs the logical O and, accordingly, the output of the AND 6 element also O. As a result, the logical inputs O are applied to the inputs of the OR 14 element (in other sources, elements AND 6 at the outputs form only O, since their corresponding triggers 10 have the level of logic O at the outputs. From the output of element OR 14, the first input of element AND 15 receives a zero signal, and the second - a single signal from the generator 12. As a result at the entrance Lok control 21 through OR gate Polling 22 enters a zero signal and the output block has the same binary code of 0000 ... 1. Thus, the unit 19 again polls the first source line for a wok.

If the reversible counter 8, after running the viitani mode, does not contain any applications, i.e. in this case, the imitation of the buffer zone of the first source from the application is simulated, the OR-NOT 7 element generates a logical 1 at the output, which passes the AND 6 element and enters the first input of the OR 14 element (O inputs are given to the other inputs). As a result of this signal about the resolution of the survey about

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It goes not only to the interrogation block, but also to the interrogation control block 21, which outputs the code 000 ... fO at the outputs, i.e. The second source queue is already polled. Also, a single signal comes from the input of the element OR NOT 7 to the first input of the counter 1 1 and resets it to zero

10 state.

Thus, there is a simulation of the arrival in the source of a group response message, the release of the buffer memory of the first source and

15 switch for polling to the buffer zone of the second source.

At the end of each survey, block 19 outputs a logical O to the third input of block 4 of the shift in each source nickname. As a result, after the arrival of the next clock pulse, they are followed by the sequential recording of bids from the generators 5 into the shift registers (Fig. 2).

25, provided that their respective counters 11 s. Contain no more than two applications.

Thus, the proposed device implements the group discipline

-JQ source service quotation, and

therefore, it is possible to simulate the functioning of closed QS with a finite number of homogeneous sources, including buffer memories and service with Mbtx with cyclic discipline group

howl dispatcher.

Claims (1)

Invention Formula 40 Device for simulating sis45 a queuing system containing a clock generator, an AND element, five OR elements, a random time delay block, an AND group of groups, a service enable signal generator, a polling unit consisting of a trigger, a delay element, an OR element, and a group of delay elements, my trigger output through a delay element is connected to the first input of the OR element of the polling unit, the output of which is connected to the zero input of the trigger of the polling unit of M sources of the current, each of which contains a pulse generator for 55 wok, b a shift lock, a trigger, three AND elements, an NAND element, an ISH-1-NOT element, a pulse counter and a reversible pulse counter in each source50 71 The output of the first element I is connected to the information input of the shift unit, the output of the first bit of which is connected to the counting input of the pulse counter and the summing input of the reversible pulse counter, the bit outputs of which are connected respectively to the inputs of the element OR NOT, subtracting the input of the reversible counter connected to the output of the second element AND its source, the output of the element OR is NOT connected to the first input of the third element AND its source, and the installation input of the pulse counter, bits The e outputs of which are connected respectively to the inputs of the NAND element, the output of which is connected to the first input of the first element AND its source, the second input of which is connected to the output of the pulse generator of the voltage, the direct output of the trigger is connected to the first input of the second element And and the second to the input of the third element AND its source of the application, the outputs of the third element AND all sources of the application are connected respectively to the inputs of the first element OR device, the output of which is connected to the first input of the element AND device, output which is connected to the first input of the second IL element of the device, the second input of which is the installation input of the device, and the third input is connected to the first information output of the service enable signal generator, the clock input of which is connected to the output of the pulse generator, the output group of which is connected respectively to the clock inputs blocks of shifting sources of the source, the overflow outputs of which are connected respectively to the inputs of the third element of the IL device, information output unit and the shift of each source of the quota is connected to a single input of the trigger of its source quotation and corresponding 87AO8 input of the fourth llli element of the device, the output of which is connected to the input of a random time delay block, the output of which is connected to the first input of the fifth UT element of the device, the second input of which is the device start input, and the output of the fifth element of the O1 the inputs of the second elements AND of all sources of the order and the first input of the trigger of the service enable signal, the second trigger input of which is connected to the output g of the third element OR device, the second informational output of the service enable signal generator is connected to the second input of the device AND device, the zero inputs of triggers of all sources, a single ry input of the trigger and the inputs of the delay elements of the polling unit group, the forward output of which is connected with block shift inputs 5 shift of all sources of the order, the output of the K-th element of the delay of the polling unit group (, M) is connected to the first inputs of the K-elements And all groups of the device, the outputs of the elements AND K-and the group are connected respectively to the discharge inputs of the shift unit K- source of the application, characterized in that, in order to expand the field of application of the device by simulating mass 5 service with a cyclic group dispatch discipline, it additionally contains a polling control unit consisting of an annular shift register and a decoder, the inputs of which are connected respectively to the bit inputs of the annular shift register, and the output of the second NW device of the device is connected to the shift input of the ring 5 of the shift register of the polling control unit, the K-th output of the decoder of which is connected to the second inputs of the elements of the K-th group of the device. 0 0 Feed } nineteen From (rormiroditel / 4fJ shFig .Z " / G 4 1 /  Overall  / spgnnaM / 7 elenontob / f Soros .4f