RU1783539C - Device for modelling of queueing systems - Google Patents

Abstract

The invention relates to specialized computing tools and can be used to simulate the operation of queuing systems. The purpose of the invention is to expand functionality by simulating the adaptation of the number of channels used to the intensity of the input stream per wok. The device comprises five triggers, six OR elements, seven AND elements, an input w / o generator, a pulse generator, two registers, four comparison circuits, three totalizing counters, a reversing counter, two delay elements, two NOT elements, a wok distribution unit, wok service channel group; random service pulse generator. The invention allows to expand the functionality of the device by providing an automatic solution to the problem of determining the rational number of channels in mass-service systems, in which all applications received must be served without loss per simulation cycle. 1 ill. sl c

Description

The invention relates to specialized computing tools, and in particular, to devices for simulating queuing systems.

The purpose of the invention is to expand functionality by simulating the adaptation of the number of channels used to the intensity of the input stream per wok.

The device comprises first 1 and second 2 triggers, second 3, first 4 and third 5 OR elements, a reversible counter 6 for the number of occupied service channels per wok, first element And 7, a distribution block for wok 8, consisting of a clock generator 9, element And 10, counter 11, decoder 12, type-setting floor 13, group

Service channels 14 for each of which consists of I-15-18 elements, OR element 19, delay element 20, trigger 21 and pulse shaper 22, a random service pulse generator 23 consisting of a random pulse stream generator 24, delay elements 25 and type-setting field 26, third trigger 27, with inputs 28, 29 setting the operating mode of the device, the input stream generator for wok 30, second 31, third 32 and fourth 33 elements And, fourth 34 and fifth 35 triggers, fifth 36, sixth 37 and seventh 38 elements And, fourth 39, fifth 40, sixth 41 OR elements, pulse generator 42, third 43, second 44, first 45 and fourth 46 comparison circuits, second 47 and first 48 RE elements, second 49 and

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the first 50 delay elements, the third 51, the first 52, the second 53 totalizers, the first 54 and second 55 memory registers, input 56 sets the initial number of service channels per wok, input sets the time of the simulation cycle 57, input 58 sets the number of simulation cycles, input 59 device startup. Before starting the simulation, triggers 1,2, 34, 35, counters 6, 11, 51, 52, 53, registers 54 and 55 are set to zero. The state of trigger 27 is indifferent. Triggers 21 are set to single states. At input 56 on, the counter 51 is written per-; the initial number of service channels, starting from which a rational number of service channels is sought. At input 57, a time code of the current simulation cycle is written to register 54. At input 58, a code for the number of simulation cycles (based on the required reliability of the simulation results) is entered into register 55. A signal is given at input 28 or 29, depending on whether the random or deterministic service time for an overnight stay needs to be taken into account in the simulation. A simulation start signal is provided at input 59 and, having passed the OR element 39, sets the trigger 35 to a single state. Since all channels 14 are free, an enable signal is present at the output of the And 37 element, then the enable signal from the direct output of the trigger 35 through the open And 36 element is supplied to the single state of the trigger 34 and to the summing input of the counter 53, where the edge of this signal, one is written to counter 53 (increasing the value of counter code 53 by one), and also to set the trigger 35 to zero. The enable signal from the output of the single state of trigger 34 opens the And 33 element for the passage of pulses from the gene Rathore 42 to a summing input of the counter 52, which is formed in the current time code cycle; at the same time, the I 31 element opens the same signal for passing the input stream signals behind the generator 30. The generator 30 applications pass through the I 31 element and the open I 7 element to the single input of trigger 1 and to the summing input of the reverse counter 6. As soon as any of the channels ends the service, the signal in the form of a pulse from the output of this channel goes to the corresponding input of the OR element 5, from the output of which it passes to the subtracting input of the reverse counter 6, the value of the number of woks, the count by 6, decreases by one. Distribution of reservation between free channels is carried out by the block

8 as follows. In the period between receipts for woks, trigger 2 is in a single state, and signals are polled for free channels from a clock generator 9 through an open element And 10

arrive at the summing input of the counter 11, which at its outputs generates binary codes of the numbers of the service channels from 1 to K, where K is the current value of the code on the counter 51. At the time of coincidence

codes at the counters 11 and 51 at the output of the comparison circuit 43, a high-level signal is generated which, with a delay at the delay element 50, is sufficient for a time to determine the free

channel, is supplied to the input of setting the zero state of the counter 11; on the edge of this signal, counter 11 is reset, and the cycle of generating service channel numbers at the bit outputs of counter 11 is repeated. The binary codes of the service channel numbers from the counter 11 are sent to the decoder 12, from the outputs of which through the dialing field 13 (switching on the dialing field 13 is determined by the polling of the service channels) the polling signals are sent to the second inputs of the corresponding AND elements 15 of the channels 14 Wok service. When the first random coincidence on one of the AND elements 15 of two signals — the free channel signal from the output of the single state of the trigger 21 of the corresponding channel and the polling signal from block 8 — at the output of the corresponding element And 1 b of the service channel 14

A signal appears which arrives through the OR 4 element to the input of setting the zero state of trigger 2. Trigger 2 with this signal is set to zero and prohibits polling pulses

appear at the output of element A 10 of the wok allocation unit 8. Thus, the search for a free channel in the period between acquisitions ends, as a result of which two signals of a free channel signal and a polling signal are present at the output of one of the AND elements 15. Received an application from the generator 30 through the open element And 7 sets the trigger 1 in a single state, in which

the signal from its output goes to the inputs of all elements of And 15. If three of the signals coincide at one of the And 15 elements - the input application from trigger 1, the signal of the free rope from the corresponding

trigger 21 of the polling signal from block 8 - on

the output of this element And 15 there is a signal (application), which is fed to the input of the corresponding delay element 20 of the service channel and at the same time through the element OR 3 sets the trigger 1 to the zero state and to the single state of the trigger 2. Interrogation signals free service channels from the generator 9 through the open element And 10, the counter 11, the decoder 12 and the dial field 13 come from block 8 to the corresponding inputs of the elements And 15 to search for the next free channel in the period between receipts for woks. Thus, the application received from the output of one of the elements And 15 to the input of the corresponding delay element 20 of the service channel for the wok sets the trigger 21 to zero. The corresponding signal about the channel occupancy from the direct output of the trigger 21 is fed to the inputs corresponding elements And 16 and 15. Serving the application of service channels for wok 14 can occur in two modes: a mode with a determinate service time equal to the delay time in the delay element 20; the mode with random service time determined by the generator 23. The control of the service mode is carried out by the trigger 27. Setting the trigger 27 in one or another state is carried out by signals arriving at the corresponding inputs 28 and 29. When the trigger 27 is in a single state, when the output to the input of the element And 18 of the service channel for wok 14 receives an enable signal, servicing of applications is as follows. The pulses from the output of the generator 23 are fed to the inputs of the And 18 elements and then through the OR 19 element to the trigger input Step 21. When the trigger 21 transitions from the zero state (channel busy state) to the single (free channel state), the end of service pulse appears at the output of the pulse former 22. When the trigger 27 is in a zero state, a single (enable) signal from its output opens the wok service element And 17, and wok service in this channel occurs with a constant service time. In this case, the next application enters the corresponding service channel for the application, where it is fed to the input of the delay element 20 and the input of the trigger 21, bringing it to the zero state. After the delay time, this application through the elements And 17 and OR 19 arrives at the other input of the trigger 21, bringing it into a single state, which simulates the moment of the end of service of the applications in this channel. In the case when on the reverse counter 6, as a result of transferring from the generator 30, the code value reaches the value K, where K is the current code value on the counter 51, a low signal is generated at the output of the comparison circuit 44, which closes the And 7 element and through the HE 48 element opens the AND 32 element. This situation indicates that the performance of the simulated system is insufficient to process the entire input stream in advance during the simulation cycle. Therefore, the next pulse of the generator 30 through the open elements And 31 and 32 is fed to the summing input of the counter 51, increasing the value of its code by one. This simulates an increase in the number of service channels per unit, i.e., system performance is increased. The same pulse from the output of the And 32 element arrives at zeroing the counter 53, on which the code of the current number of cycles is generated, and zeroing it. Thus, the count of the current number of simulation cycles starts again. At the same time, the same signal from the output of the AND 32 element, passed through the OR 41 element, sets the trigger 34 to the zero state, which stops the pulses of the generators 30 and 42 from passing through the And 31 and 33 elements, respectively, and passes through the OR 40 element and the delay element 49 during transients in the counter 52, it enters the zero-state input of the counter 52, nullifies it, and after passing through the AND 38 element, it enters the OR element 39 as an input to the simulation. That is, the system operation simulation cycle begins, but with a number of service channels increased by one (compared to the previous simulation cycle). An increase in the number of service channels occurs until all applications are serviced without loss on a given number by a simulation cycle, or the required number of service channels to satisfy the entire input stream without loss exceeds the acceptable value. If during the simulation cycle all applications of the generator 30 are serviced without loss, then at the time of equal time codes on the counter 52 and the register 54 at the output of the comparison circuit 45, a high-level signal is generated, which, passing through the element - OR 41, is fed to the installation input trigger state 34 by setting it to

zero state and thereby ending the simulation cycle. The same signal, passed through the OR element 40, with a delay on the delay element 49, nullifies the counter 52, preparing it for the beginning of the next cycle, and, having passed through the And 38 element, is supplied to the OR element 39 as a signal to start modeling on a new cycle. At the same time, the counter 51 will store the code of the number of channels at which the entire input stream is served without loss in the previous simulation cycle, and the code of the number of the current simulation cycle will be generated at counter 53. If the codes on the counter 53 and the register 55 are compared, then the output of the comparison circuit 46 displays a high-level signal (enable), which closes the AND element 38 through the element 47, which indicates that the specified number of simulation cycles has passed , and on one of them there was no loss for the wok of the input stream. Thus, if on this simulation cycle all input stream orders are processed without losses, the signal from the output of the comparison circuit 45 (when the cycle time codes on counter 62 and register 54 are compared) will set trigger 34 and counter 52 to zero states. and the input of the OR 39 element as a signal of the beginning of the simulation will not pass, since the And 38 element is closed. As a result, the simulation will end, but the counter 51 will be fixed with a rational number code by a structural service channel) QS, at which the input flow an application is processed without loss in a given operation cycle with the required reliability. Otherwise, the process of determining the rational number of channels for processing without loss of input stream per wok per operating cycle will continue. The end of the simulation can occur in case of overflow of the counter 51, which indicates that the input stream cannot be completely processed without losses due to an increase in the number of service channels, the number of which is limited by the value for the device. In this case, the high level signal from the overflow output of the counter 51 enters through the OR element 41 to set the trigger 34 to the zero state, which completes the simulation process.

Claims (1)

The claims System Simulator queuing service containing three trigger, random pulse generator service, three OR elements, an input flow generator for wok, the first AND element, a reversible counter of the number of occupied service channels for a wok and a group of service channels. for a wake, the output of the first element And is connected to the summing input of the reverse counter of the number of occupied service channels for woks and to a single input of the first trigger, the direct output of which is connected to 0 information inputs of service channels for the wok of the group, a distribution block for wok consisting of series-connected clock pulses, an element And, a pulse counter, a decryptor and a dial field, the outputs of which are connected respectively to the inputs of the polling of service channels for the wok of the group, alarm outputs about the free state of which are connected respectively to the inputs of the first OR element, the output of which is connected to the zero input of the second trigger, the direct output of which is connected to another input Entry AND of the distribution block for the wake, the zero input of the first trigger and the single input of the second trigger are connected to the output of the second OR element, the inputs of which are connected respectively to the signaling outputs about the acceptance of service channels for 0 wok, the single and zero inputs of the third trigger are inputs of setting the operating mode of the device, the direct output of the third trigger is connected to the inputs of the random time setting5 of the service of all service channels for the group wake-up, the inputs of the constant time setting of the service oryh connected to the inverted output of the third flip-flop, the outputs of the service 0 for servicing service channels, for serving groups, respectively, are connected to the inputs of the third OR element, the output of which is connected to the subtracting input of the reverse counter of the number of occupied service channels5 for no wise, and the outputs of the random service pulse generator are connected respectively to the inputs of the formation of a random service channel service time interval for VSGK, which implies that, in order to expand the functionality of the device by simulating the adaptation of the number of channels used to Intensity input for wok, it 5 additionally contains the second to seventh AND elements, two delay elements, four comparison circuits, two memory registers, three totalizing counters, two NOT elements, the fourth, fifth and sixth OR elements, fourth and fifth triggers and a pulse generator, wherein the output of the input stream generator behind the wok is connected to the first input of the second element And, the output of which is connected to the first inputs of the first and third elements And, the second input of the second element And and the first input of the fourth element And are connected to the direct output of the fourth trigger, the output of the pulse generator is connected to the second input of the fourth element And, the output of which is connected to the counting input of the first totalizing counter, the bit outputs of which are connected respectively to the information inputs of the first groups of the first comparison circuit, the information inputs of the second group of which are connected respectively to the bit outputs of the first memory register, the bit inputs of which are inputs of the set time of the device simulation cycle, the first input of the fourth OR element is the device start input, and the output of the fourth OR element connected to a single input of the fifth trigger, the direct output of which is connected to the first input of the fifth element And, the second input of which is connected to the output of the sixth element And, the inputs of which are connected respectively, with the outputs of the signaling of the occupancy of service channels for the group wake up, the output of the fifth AND element is connected to the single input of the fourth trigger, the zero input of the fifth trigger and the counting input of the second totalizing counter, whose zeroing input is the first inputs of the fifth and sixth elements OR and the summing input of the third summing counter is connected to the output of the third AND element, the bit inputs of the third summing counter are the inputs of setting the initial number of service channels for the device The digital outputs of the third totalizing counter are connected respectively to the information inputs 5 of the first group of the second and third comparison circuits, the information inputs of the second group of the third comparison circuit are connected respectively to the digital outputs of the counter of the allocation block for the application, and the output of Equal to the third comparison circuit is connected to the input of the first delay element, the output of which is connected to the installation input of the counter of the distribution unit for the wok, the output is 5 of the second comparison circuit is connected to the second input of the first AND element and the input of the first element NOT, the output of which is connected to the second input of the third AND element, the output is equal to the first comparison circuit connected to the second inputs of the fifth and sixth OR elements, the third input of the sixth OR element is connected to the overflow output of the third totalizing counter, and the output of the sixth OR element is connected to the left input of the fourth trigger5, the output of the fifth OR element is connected to the input of the second delay element, the output of which is connected to the installation input of the first adder and the first input of the counter 0 of the seventh element And, the second input of which through the second element is NOT connected to the output of the Fourth comparison circuit, and the output of the seventh element And is connected to the second input of the fourth OR element, the information inputs of the first and second groups of the fourth comparison circuit are connected to the bit outputs, respectively, of the second summing counter of the second memory register, the bit inputs of which 0 are inputs for setting the number of simulations of the device. w -ft 3635 39 68