SU1124320A1 - Device for simulating queueing system - Google Patents

Abstract

1. A DEVICE FOR MODELING MASS SERVICE SYSTEMS, containing a generator of a voltage whose output is connected to the information input of the first prohibition element, the first input of the first element AND and the counter input for the wok, the output of the first prohibition element is connected to the first input of the first OR element, the output of which is connected with a summing input of a reversible counter, the number of occupied channels, the subtracting input of which is connected to the output of the second element OR, and the bit outputs are connected respectively to the inputs of the first many And, the output of which is connected to the control input jnepBoro of the prohibition element and the second input of the first element And whose output is connected to the input of the counter lost, the third element And, the block of random time delays, the output of which is connected to the first input of the second element OR, the generator of priority requests, the output of which is connected to the input of the priority counter for the wok, the first input of the second element AND, and the information input of the second element aapret, a reversible counter of the number of priority serviced wok, the output of the second element I is connected to the input of the counter of lost priority requests, the third element of the prohibition, characterized in that, in order to expand the functionality by simulating absolute priority of service, it additionally contains a counter of the number of incompletely served applications, the second multi-input the element And the reversing block of random time delays, and the output of the reversing block random | time delays are connected to the eye input of the second element OR, summing the input of the reverse random delays block is connected to the output of the first prohibition element, and the subtracting input of the reverse block of random time delays is connected to the input of the counter of the number of incompletely served by the wok and the output of the third element I, the first input which is connected to the output of the first multi-input element And and the information input of the third prohibition element, the second input of the third element And is connected to the summing input of the reverse Nogo counter number priority applications are serviced, output of the second element prohibition input of the random time delays and data input of the third element prohibition, the output of which is connected to a second input of said first OR gate, the output of random time delay block is connected to a subtracting input of down counter

Description

the number of priority serviced requests, the bit outputs of which are connected respectively to the inputs of the second multi-input element I, the output of which is connected to the control input of the second prohibition element and the second input of the second element I, 2. The device according to claim 1 a random time delay block contains a common element NOT, a common OR element, n channels, each of which consists of a random delay element, a trigger, two AND elements and an NL element, the output of which is connected to the first input trigger A second input coupled to an output of the first AND gate and the input start random delay element whose reset input and a first input of the OR element connected to the output of the second AND gate, the second input element. OR is connected to the output of a random delay element and the corresponding input of a common OR element, the output of which is the output of a block, n-1 control nodes, each of which contains two OR-NOT elements, two OR elements and two NOT elements, the first input of the first the element OR NOT and the first input of the first element OR of the first control node are connected to the output of the common element NOT and the first input of the second element AND the first

channel, the first input of the second element OR NOT and the first input of the second element OR of the first node of the control are connected to the input of the common element NOT, the first input of the first element AND and the output of the first channel trigger, the first: the inputs of the first element OR NOT and the first element OR The K-th control unit is connected to the output of the first OR element (K-1) of the control unit (, p), the first inputs of the second OR-NOT element and the second element OR K-th control node are connected to the output of the second OR element (K- 1) of the control unit, in each control unit the second inputs The first and second elements OR are connected respectively to the outputs of the first and second elements NOT, the outputs of the first and second elements OR NOT of the K-th control unit are connected to the first inputs of the second and first elements of the AND (K + 1) -th channel, respectively, and the output of the trigger The Kth channel is connected to the second inputs of the first and second IZH-NOT elements and the inputs of the first and second elements of the NOT (K-1) th control node, the combined second inputs of the first elements AND of all channels are the summing input of the block, and the combined second inputs second element And in all the channels are input vychitayupschm reversible block of random delay.

The invention relates to computing technology and can be used in the study of queuing systems (QS),

A device for simulating a QS containing a logic unit, an input flow generator, a control unit, a clock pulse generator, counters, a block measuring the time of service channels J are known.

The disadvantage of this device is low modeling accuracy.

Closest to the proposed invention is a device for simulating a QS containing a generator of a wake, the output of which is connected to the input of the first prohibition element, the first input of the first element AND and the input of the first counter, the output of the first prohibition element through the first element OR is connected to the summing input of the first reversing a counter whose bit outputs are connected respectively to the inputs of the decoder and multi-input element AND whose output is connected to the control inputs of the first and second recording elements The second and second inputs of the first and second elements are And, whose outputs are connected respectively to the inputs of the second and third 31 counters, the output of the second generator is connected to the first input of the second element And, the fourth counter and the second prohibition element, the output of which is connected to the second input of the first the OR element and the first input of the second OR element, the second input of which is connected to the output of the second element AND and the summing input of the second reversible counter, the summing input of which is connected to the output of the third element AND and the bit outputs through the multi-input element OR are connected to the first input of the third element AND and the control input of the third prohibition element, the input of which is connected to the output of the first block of random time delays, and the output to the first input of the third element OR, the second input of which is connected to the output of the second block of random time delays, the output of the third element OR is connected to the subtractive input of the first reversible counter, the output of the second prohibition element is connected to the second input of the second element OR, the output of which is one with the input of the second block of random time delays, the decoder output through the switch connected to the input of the second trigger generator for wok Zj. However, in real conditions there are situations when some type of application has absolute priority, i.e. terminate the implementation of lower priority for wok. The known device does not allow to model such QS. The circuit of the invention is the extension of the functionality of the device by simulating the absolute priority in the maintenance of a quotation. The goal is achieved by the fact that the device for simulating queuing systems, containing the generator of the wok, the output of which is connected to the information input of the first 3-element, the first input of the first element I and the input of the counter of the wok, the output of the first prohibition element is connected to the first to the input of the first OR element, the output of which is connected to the summing input of the reversible counter of the number of occupied channels, the subtractive input of which is connected to the output of the second ORB element, and the bit outputs under 20 are connected Essentially to the inputs of the first multi-input element And, the output of which is connected to the control input of the first prohibition element, the second input of the first element And, the output of which is connected to the input of the counter lost, the third element And, a block of random time delays, the output of which is connected to the first input the second element OR, the priority request generator, the output of which is connected to the input of the priority counter for the wok, the first input of the second element AND, and the information input of the second prohibition element, a reversible counter the serviced priority requests, the output of the second element I are connected to the input of the counter of lost priority applications, the third prohibition element, the counter of the number of incompletely served applications, the second multi-input element AND and the reversible block of random time delays are introduced, and the output of the reversible block of random time delays connected to the second input of the second element OR, the summing input of the reversing unit is a case of. time delays connected to the output of the first prohibition element, and the reading input of the reversing unit random time delays are connected to the input of the counter of the number of incompletely served by the wok and the output of the third element I, the first input of which is connected to the output of the first multi-input element I and the information input of the third prohibition element, the second input of the third element I is connected to wok, the output of the second prohibition element, the input of a random time delay block and the information input of the third prohibition element, the output of which is connected to the second The primary input of the first element OR, the output of a random time delay block is connected to the subtractive input of the reversible counter of the number of serviced priority applications, the bit outputs of which are connected respectively to the inputs of the second multi-level element And, the output of the second block is connected to the control input of the second prohibition element and the second input of the second element I. In addition, the reversible block of random time delays contains a common element NOT, a common element OR n channels, each of which consists of an element of random s support, trigger-a, two elements AND and element OR, the output of which is connected to the first input of the trigger, the second input of which is connected to the output of the first element AND and the start input of a random delay element whose reset input and the first input of the element OR are connected to the output of the second element And, the second input of the OR element is connected to the output of the random delay element and the corresponding input of the common OR element, the output of which is the output of the block, control nodes, each of which contains two OR-NOT elements, two OR elements and two a NOT element, the first input of the first element OR NOT and the first input of the first element OR of the first control node are connected to the output of the common element NOT and the first input of the second element AND of the first channel, the first input of the second element OR NOT and the first input of the second element OR of the first the control unit is connected to the common element input, the first input of the first element AND and the trigger code of the first channel, the first inputs of the first OR element and the first element OR of the K-th control node are connected to the code of the first OR element (K-1) - go knot control sloth (n)., the first inputs of second OR-NO element and the second element OR-th control node connected with. the output of the second element OR (K-1) of the control unit, in each control unit the second inputs of the first and second elements OR are connected respectively to the outputs of the first and second elements NOT, the outputs of the first and second elements OR NOT K of the The controls are connected to the first inputs of the second and first emitters of the (K + 1) th channel, respectively; the output of the K-th trigger is connected to the second inputs of the first and second YPI-NOT elements and the inputs of the first and second elements (K-1 ) -th control node, the combined second inputs of the first elements And in These channels are the summing input of the block, and the combined second inputs of the second elements And of all the channels are the subtracting input of the reverse random delay unit. FIG. 1 shows the scheme of the proposed device; FIG. 2 is a diagram of a reversible block of random time delays; Fig 3 is a block diagram of random time delays. The device contains generator 1 for wok, generator 2 for priority wok, counter 3 for wok, counter A for lost wok, counter 5 for priority wok, counter 6 lost for priority wok, first 7, second 8 and third 9 prohibition elements, the first 10, the second 11 and the third 12 elements And, the reversing block 13 random time delays, the block 14 random time delays, the first and second elements OR 15 and 16, the reversing counter 17 the number of occupied channels, the reversing counter 18 the number of served priority wok, first and second multi-input ale And Options 19 and 20, a counter 21, the number of applications are fully serviced. The reversible block 13 random time delays includes p-1 control nodes 22 containing the second element IPI-NO 23, the first element of the CRPD-NOT 24, the first 25 and the second 26 elements OR, the first 27 and second 28 elements NOT, In addition, the block contains the common element OR 29 and n channels 30, each of which contains the element OR 31, the first 32 and second 33 elements AND, the trigger 34, the element 35 of the random time delay. The block also contains the summing .36 and subtracting 37 inputs and the common element NOT 38, the Block 14 random time delays contains the elements SHSh-NOT 39, the elements OR 40, the elements 41, the elements 41, the element 42, the channels 43 consisting of the elements AND 44, the trigger 45, random time delay element 46. Block 13 operates as follows. In the initial state, the output of the flip-flops 34 of all channels is high (logical unit). Each trigger 34 ensures that there is a low level (logical zero) at the outputs of the OR-NOT 24 elements whose numbers are greater than or equal to the number the corresponding trigger 34. To open each of the elements of AND 32 it is necessary to have a high level at the output of the corresponding element OR NOT 24. Therefore, if one of the channels 30 is free, let's assume with the number i, then at the output of the trigger 34; high level, which (through the sequence of elements OR 26- ,, OR-NOT 24, -, OR 26 ...) excludes the possibility of passing an impulse imitating the receipt of the application to the elements of random time delays of channels 30 with nominal i +1, ..., p. An impulse arriving at the input 36, through the open element I 32 of the first channel 30 passes to the zero input of the trigger 34 and to the input of the start of the epimete 35 of a random time delay. Until, while this impulse is not in accordance with its output, on, the output of trigger 34 is low and only the AND 32g element is open. When the next pulse arrives, an element 352 of the random time delay of the second channel 30 is activated, and at the output of the trigger 342 also a low level, etc. The impulse at the output of the element 35 of the random time delay (, ..., p), which appeared after a time equal to the random duration of the service, through the element OR 31; It arrives at the single input of the corresponding trigger 34; it transforms it into the state of a logical unit and through the OR element 29 enters the output of the block. The impulse received at the subtracting input 37 of block 13 and imitating the removal of service requests should release one of the n channels 30. This is possible if at least one of the n channels is occupied. Each trigger of the occupied channel is in logical zero and ensures the presence of a low level at the outputs of the elements OR NOT .24 with numbers greater than or equal to the number of the corresponding trigger 34 Dp open one of the elements AND 33, for example number i, you must have a high level at the output of the element OR NOT 24j . . Therefore, if channel 30 is busy; then the trigger 34j of this channel is in the state of logical zero and the signal from its output (through the sequence of elements NOT 27; "-1 OR 25;, OR-NOT 24; .,) eliminates the possibility of the passage of a pulse simulating the removal of a service request from the negative inputs of channels 43 with numbers i + l, .., p. Let i be now the smallest number of the occupied channels. In this case, only one AND 33; element is open, since all AND elements with numbers greater than i are closed with a low level triggered signal, and And 33 elements with numbers Hera 34J and smaller i are closed with high level signals from the output of the 34j triggers ( since channels with numbers smaller than i are free). Then the impulse arriving at input 37 of block 13 passes through the open element 33 to the negative input of the element 35 an accidental time delay, simulating the withdrawal of the service call, and through the element OR 31, to the single input of the trigger 34; logical unit, which means the release of one channel. Thus, block 13 makes it possible to imitate channel occupancy for servicing upon arrival of a pulse to block summing input 36, a free channel with a lower number is selected, as well as withdrawing a quitment from servicing upon arrival of a pulse to block subtracting input 37, and This channel with the smallest number, Block 14 works as follows. In the initial state, the triggers 45 of all channels are in the state of an ohmic unit. At the same time, these triggers ensure the presence of a low level at the outputs of RHINE 39 elements with numbers greater than or equal to the number of the trigger 45. To open each of the AND 44 elements, a high level signal is required at the output of the corresponding element OR NOT 39. Therefore, if one of the channels, we assume with number i, then the trigger 45j is found in the state of logical unity, and the signal from its output (through the sequence of elements OR 0j.,, .OR-NOT. 39;, OR 40 ;, OR-NOT eliminates the possibility of impulse imitating

91

the receipt for applications on the channels of the channels with numbers greater than 1. The impulse received at input 47 through the open element 44 of the first channel 43 enters the zero input of the trigger 45, and the input of the element 46 of the random time delay. As long as this impulse is not. At the output, at the output of the trigger 45, the low level is open and only the element of the second channel I 442 arrives at the next impulse, it enters the input of the element 462 of the random time delay and sets the trigger 45rt to the state zero and so on

The impulse that occurred on the passage of the element 46j after a time equal to the random duration of service sets the corresponding trigger 45 to the state of a logical unit and through the SHSh 42 enters the output of the block.

The device works as follows.

No.1 pulses from generators 1 and 2, imitating the flow of the flow, arrive at counters 3 and 5. In the case when not all channels are busy, there is no signal at the output of the multi-input element And 19, while the prohibition elements 7 and 9 are open and the elements are closed Both 10 and 12. The pulses from the generator 1 through the prohibition element 7 and the element ШИИ 15 arrive at the summing input of the counter 17 and simultaneously enter into the block 13, simulating the service process. The arrival of a pulse at the summation of the input of the counter 17 increases its code by one, which means that one channel is busy. The impulse that arrives at the input of block 13 appears at its output after a time equal to the random service duration, enters the subtractive input of the counter 17 busy channels and writes off the unit from it, thereby simulating the release of one channel. The pulses from generator 2 through the open prohibition element 8 arrive at the summing input of the counter 18, the number of served priority orders, and also through the element 9 of the prohibition and the element OR 15 to the summing input of the counter 17 of the total number of occupied channels. The same pulses arrive at the input of block 14 and after a certain time equal to a random time about

24320JO

service of the priority tppa, are fed to the subtracting input of the counter 18, i.e. Information about J total number of channels occupied is stored at any Time moment on counter 17, and about the number of channels occupied by priority applications is stored at counter 18.

If all channels are occupied, but the number of priority quotes is not equal to the number of channels, then in this case, the output of the AND 19 element is the signal that the control inputs of the 7 and 9 prohibition elements appear and for the input, j d elements AND 10 and 12. At the same time, prohibition elements 7 and 9 are closed, and elements 10 and 1Y are opened. Then the pulses from the generator 1 pass through the element AND 10 to the input of the count 2Q of the pick 4, simulating the flow of the rejected service. The same pulses are fed to the input of the counter 3 per wok.

The impulse from generator 2 is fed to the input of counter 5 and through the open element 8 of the prohibition, since there is no signal from the output of the multiple element I 20, it goes to the positive input of counter 18 and the number of served priority quotes and through the open element 12 to the input of counter 21 and subtracting input of block 13, in which it excludes non-priority payment from service. In this case, the excluded application is lost. The counting of such bids is made by counter 21. The same pulse from the output of bar 8 arrives at the input of block 14 and, after service simulation, to the subtracting counter input 18, the number of served priority bids and, through the W 16, to the subtracting input of the counter 17 busy channels. If all channels are prioritized, then signals from the outputs of the multi-input elements And 19 and 20 are generated. These signals close the prohibition elements 7 and 8 and open the elements And 10 and 11. Then the pulses from the generators 1 and 2 postzpayut counters of the number of incoming non-priority 3 and priority 5 applications and through open elements And 10 and 11 to the counters of the number of lost priority 4 and priority 6 requests for lost. In this case, all submitted applications are lost. Thus, the device allows the simulation of QS with two random flows of the application: without priority and with absolute priority. The statistical characteristics of the operation of the QS simulated by this device are calculated by known methods based on the readings of the counters of the number of incoming

t-

12

Yu

13

15

13

2012 G6 priority priority and absolute priority orders, connected directly to incoming flow generators, failed request counters, due to the lack of free channels in the system, and the incompletely served meter (no service was interrupted by the arrival). for wok with a6T priority).

18

/ "

20

1

Claims (1)

1. DEVICE FOR MODELING MASS SERVICE SYSTEMS, comprising a claim generator, the output of which is connected to the information input of the first prohibition element, the first input of the first AND element and the input of the application counter, the output of the first prohibition element is connected to the first input of the first OR element, the output of which is connected to the summing the input of the reverse counter of the number of occupied channels, the subtractive input of which is connected to the output of the second OR element, and the bit outputs are connected respectively to the inputs of the first multi-input e element And, whose output is connected to the control input. of the first prohibition element and the second input of the first element And, the output of which is connected to the input of the counter of lost applications, the third element And, a block of random time delays, the output of which is connected to the first input of the second element OR, generator priority applications, exit. which is connected to the input of the priority application counter, the first input of the second AND element and the information input of the second prohibition element, a reverse counter of the number of priority applications served, _{x the} output of the second AND element is connected to the input of the counter of priority applications lost, the third prohibition element, characterized in that, in order to expand the functionality by modeling the absolute priority in service, it additionally contains a counter of the number of incompletely served requests, the second multi-input an AND element and a reverse block of random time delays, the output of the reverse block of random time delays being connected to the second input of the second OR element, the summing input of the reverse block of random time delays is connected to the output of the first inhibit element, and the subtracting input of the reverse block of random time delays is connected to the input the counter of the number of incompletely served applications and the output of the third element And, the first input of which is connected to the output of the first multi-input element And and the information input the third prohibition element, the second input of the third AND element is connected to the summing input of the reverse counter of the number of priority requests served, the output of the second prohibition element, the input of the random time delay block and the information input is the third of its prohibition element, the output of which is connected to the second input of the first OR element, the output of the block random time delays is connected to the subtracting input of the reverse counter of the number of serviced priority requests, the bit outputs of which are connected respectively to the input m of the second multi-input element And, the output of which is connected to the control input of the second inhibit element and the second input of the second element And, 2. The device according to claim 1, characterized in that the reversible block of random time delays contains a common element NOT, a common OR element, η channels , each of which consists of a random delay element, a trigger, two AND elements, and an OR element, the output of which is connected to the first input of the trigger, the second input of which is connected to the output of the first AND element and the trigger input of the element of 'random delay and, the reset input of which and the first input of the OR element are connected to the output of the second AND element, the second input of the OR element is connected to the output of the random delay element and the corresponding input of the common OR element, the output of which is the output of the unit, p-1 control nodes, each of which contains two elements OR NOT, two elements OR and two elements NOT, the first input of the first element OR NOT and the first input of the first element OR of the first control node are connected to the output of the common element NOT and the first input of the second element AND of the first channel, the first the course of the second OR-NOT element and the first input of the second OR element of the first control node are connected to the input of the common NOT element, the first input of the first AND element and the trigger output of the first channel, the first inputs of the first OR-NOT element and the first OR element of the Kth control node are connected with the output of the first OR element (K-1) of the control node (K = 2, p), the first inputs of the second OR-NOT element and the second OR element of the K-th control node are connected to the output of the second OR element (K-1) - th control node, in each control node the second inputs of the first and second of the first OR elements are connected respectively to the outputs of the first and second elements NOT, the outputs of the first and second elements OR NOT of the K control node are connected to the first inputs of the second and first elements of the And (K + 1) channel, the trigger output of the K the channel is connected to the second inputs of the first and second elements OR NOT and the inputs of the first and second elements NOT (K-1) of the ~ control node, the combined second inputs of the first elements AND of all channels are the summing input of the block, and the combined second inputs of the second elements AND of all channels subtraction input are reversible block of random delay.