SU1218386A1 - Device for checking comparison circuits - Google Patents

Abstract

The invention relates to the field of automation and computing. The purpose of the invention is to increase the reliability of the control. The device contains a memory block, a micro-command register, a multiplexer, an address register, a trigger, a clock pulse generator, two shift registers, a comparison element, a controlled comparison circuit, an analysis unit, two AND elements, two N1-NI elements, three I. There is no verification of the comparison circuit in four modes. In the first mode, the number L 0 is fed to the first group of inputs of the comparison circuit, and the number B, in which the unit is present in only one bit, is fed to the other using the shift register. In the second control mode, a number containing a unit in bits A is fed, and to another input a number in which the unit is contained in the penultimate bit, and so on, until that unit has been rewritten in the first bit of the shift register. In this mode, the equality A B of all inputs Qi, b is checked. The third and fourth modes are equivalent to the first and second. Due to the sequential control, the minimum set of checks is implemented, ensuring the control of all the signal-shaping circuits. Л.В, А в, 5 Il. i (Л С

Description

one

1 invention relates to automation and computing technology and can be used in the implementation of test diagnostics tools for blocks of discrete technology.

The aim of the invention is to improve the reliability of the control.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - timing diagram of the clock pulse generator.

The device for control of comparison circuits (Fig. 1) contains a controlled comparison circuit 1, a memory block 2, an address register 3, a microinstruction register 4, a shift register 5.6, a trigger 7, a clock pulse generator 8, a multiplexer 9, an element U cepEgenp, analysis block 11, containing an AND-OR NOT 12 element, OR elements 13, 14; elements 15, 16, elements tl 17, 18, elements ШШ 19, 20, run .. start 21, error output device 22, first to fourth outputs 23-26, memory block, first de, t) 1st outputs 27-35 of the register of 4 micro-commands, the first-third outputs 36- 33 of the comparison circuit, the outputs 39-41 of the high register register 5, the low and high register register 6, respectively, the outputs 42-44 of the clock generator 3 (outputs of the address field of the memory 23, the sign of the modification of address 24, the sign of the next address of the microcommand 25, the output 26 of the control field, the output 27 of the sign of resetting the first shift register, output 28 of the permission indication output 29 of the comparison indication, output 30 of the reset symptom of the second shift register, output 31 of the resolution indication, output 32 of the noncomparison characteristic, output 33 of the analysis feature, outputs of the feature of the logic conditions 34, sign of the end of the control 35, output Equal 36, output Equal 37, output It is unequal 38, the outputs of the high bit, the outputs of the low and high bits of registers 5 and 6, respectively 39-41, the outputs of 42.44 clock generators The device works as follows.

In the initial state, all elements of the device memory are in the zero state. FIG. 1, the reset circuit conditionally is not shown.

83862

The device checks the comparison circuit 1 sequentially in the following modes.

First Mode At the first entrance

Circuit 1 is supplied with the number A 0, and using shift register 6 is sequentially formed and fed to the second input of circuit 1, the number B contains a unit only in one bit 0 de from to. As a result of this mode, the operability and correctness of the response of circuit 1 to the unit signal on all inputs of the number.

s second mode. The number containing the unit in the highest bit (DV, 1) is set to the input to the circuit 1, and the numbers containing the unit

0 in bits a,.,., C. After that, the number C -1 is entered at the input B, and the numbers containing one in bits 1, cia, are entered at the input A sequentially. . . , (and so on

5 b 1 1 and). As a result of performing this mode, the correctness of the formation of the signal АВ by circuit 1 for all inputs, i 1 п and the correctness of

0 forming by circuit 1 a signal for all pairs of bits Bj, Q; , i 1, n, aj 1, i. This allows you to effectively test the performance of the lower-order blocking circuits of the older bits of all inputs of circuit 1.

The third mode. This mode is completely equivalent to the first mode. The input of the circuit 1 is supplied with the number В - О, and the input D is given in succession to the numbers containing o t-, -i 1, ..., Q (-, - 1. As a result of this mode, the operability of all circuits forming the signal A of the circuit 1 through all the inputs of the number A.

Fourth mode. This mode is equivalent to the second control mode. The difference is that for each number A, containing one unit (a, 1, a. 1, ..., a -1), numbers B are sequentially formed, containing one in bits bj, j 1, i, if a | 1. Due to the implementation of this mode, the operability of the signal shaping circuits АВ by circuit 1 and the operability of blocking circuits by the senior bits of the younger ones when generating a signal through all the inputs of circuit 1 are checked.

five

five

0

five

Sequential control of circuit 1 using the proposed device provides a significant increase in the reliability of control results with high speed through the implementation of a minimum set of checks that ensure control of all signal generation circuits, A, as well as the low-order blocking circuits of the older ones.

In tab. 1 shows a table of codes of numbers A and B, successively supplied to the inputs of circuit 1, when implementing the first to fourth control modes (with n 4).

Consider the operation of the device in the listed modes.

According to the Start signal, which arrives at the device input 21, the trigger 7 is set to one state and starts the generator of 8 clock pulses, which begins to form sequences of clock pulses.

At the output 35 of the register of 4 microcommands there is a zero code, therefore the output signal of the multiplexer 9 is equal to one, and the element And 18 is open. The first clock pulse from the output 42 of the generator 8 clock pulses is fed to the sixth input of the analysis block 11, which controls the correctness of the operation of the circuit 1 on the numbers L B 0. At the same time, this clock pulse goes to the synchronization input of the register 3 address on its trailing edge in the address register 3 is written the address of the first micro-command, which is stored in a cell with a zero address. As a result of this, the first micro-command is read out from the memory block 2. On the falling edge of the second clock pulse from the output 43 of the generator 8 clock pulses, its micro-operation part and the code of the checked logical condition are written to the register of 4 micro-instructions. As a result, the device enters the first control mode.

At the output 32 of the register of 4 micro-instructions, a single signal appears, which opens the element AND 16, to which the pulses from the output 44 of the generator 8 clock pulses are sequentially applied. As a result, a unit is written to the low-order bit of shift register 6, which

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successively shifted toward the higher bit. At each position of the unit in the register 6 shift to the sixth input of the analysis block 11

5, a clock is outputted from the output 42 of the 8 clock pulse generator, which follows every time after the pulse at the output 44 of the clock generator 8 (see Fig. 2). AT

10, this checks the health of circuit 1 in the first monitoring mode over all bits of input B. The logical condition code that arrives at multiplexer 9 switches the output 41 of the shift register 6 to the INPUT) of the AND 18 element. Therefore, until the unit in register 6 reaches its highest bit, the address in register 3 of the address

20 of the next microinstruction ..

After the occurrence of the unit in the high order of the 6th shift register, the element And 17 will open, and the next pulse from the output 42 of the generator 8 clocks will write to the register 3 addresses, the address of the next microcommand, and its operational part with the code of logical conditions on the clock pulse from the output 43 of the generator 8 clock pulses are written to the register of 4 micro-instructions. As a result, the device will switch to the second control mode.

At the output 29 of the register of 4 microinstructions, according to a VITS, a single signal that will open the element AND 15, and in the lower bit of the register 5 of the shift, a unit will be written, which will be sequentially shifted towards the higher order until it reaches it (A B). In each clock cycle, the clock pulse from the output 42 of the generator 8 clock pulses will monitor the correct operation of the circuit 1 by the analysis unit 11. The logical condition code will configure multiplexer 9 so that the comparison element 10 is connected to the input of the AND 18 element. Therefore, the next clock pulse will pass

50 to the input of synchronization of register 3 only with the codes of numbers A. V 1000. ... 0. According to this Pulse, the next microinstruction will be read out from memory 2, and at outputs 27,

55 31, 32 registers of 4 microinstructions according to the TC single signals. On these signals, the shift register 5 is reset to zero, and in shift register 6

thirty

35

40

45

the unit of the senior (nth) bit will shift to the (n - 1) th bit (reverse shift). After that, the next pair of clock pulses from the output 42 and 43 of the generator 8 clock pulses will read the next microcommand, output 29 of register 4 microcommands will receive a single signal, and the test cycle of circuit 1 will repeat until the codes A 6 010 .., 0 match.

When A B to the register of 4 micro-commands, the micro-command for checking the logical condition b 1 will be read; for which, using multiplexer 9, trigger output 7 (constant 1) will be connected to the input of AND 18, and output 24 of memory 2 will generate a single signal that will open AND 17, allowing the address to be modified by the value of the lower bit of register 6 ( output 40). With bi, there will be no modification, in the register of 4 micro-commands, the micro-command of reset-register 5 and a shift by one to the right of the contents of the register b of the shift will be read again, and the device operation cycle will be repeated. This will continue until equality A -6 is obtained.

00001, i.e. unit in register

6 shift does not reach the low bit. After that, the address of the next microcommand will be modified by a single lower-order value of the shift register b, and the device will be removed from the cycle (see Fig. 1). In register

4 micro-commands will be read the next micro-command to reset the shift register b, and then the shift micro-command unit in shift register 5. The device enters the third control mode.

The operation of the control device in the third and fourth modes is similar to its operation in the first and second modes, respectively. The difference is that the register functions

5shifts in these modes completes the shift register b and vice versa, respectively, microcommands, readable in these modes, contain microoperations that are inverse to the preceding ones.

At the end of the fourth Control mode, which will also be characterized by the condition А ВО 0. ..01, a micro-command will be read into register 4 of micro-commands containing the end of the micro-operation. At the output 34 of the register of 4 microinstructions, a single signal is passed, which, having passed through the SLI element 19, will return the trigger 7B to its original state, and the device will stop working.

If, in any device operation cycle, the analysis unit 11 detects an incorrect operation of the monitored comparison circuit 1, a single signal is output at its output that stops the operation of the device (resets the trigger 7) and passes to the output 22 of the device, signaling the incorrect operation of the circuit 1 .

In tab. Figure 2 shows one of the possible options for flashing memory 2 to implement all four monitoring modes.

As follows from the table. 2 the contents of the memory cells of block 2 does not depend on the size of the checked circuits 1 and occupies a very small amount of memory.

Claims (1)

Invention Formula A device for control of comparison circuits, containing a controlled comparison circuit, first and second shift registers, triggers, clock generator yi analysis unit, the device start input connected to a single trigger input, the output of which is connected to the start input of the clock generator, first and second output groups the second shift registers are connected to the first and second groups of information inputs of the controlled comparison circuit, the output is equal to, and two outputs are unequally connected to the first, second, and third inputs of the block analysis, respectively, the output of which is the output of a device error, that is, so that, in order to make the control more reliable (, it contains a memory block, an address register, a microinstruction register, a multiplexer, a comparison element, the first and second elements OR NOT, the first, second, third and fourth elements AND, the first and second elements OR, and the outputs of the micro-command register reset indications are connected to the reset inputs of the first and second shift registers, respectively, the outputs of the micro-command register enable attributes Nene with entrances records of the first and second shift registers, respectively, the output groups of the first and second shift registers, with the exception of the lower-order outputs, are connected to the first and second groups of information inputs of the comparison element and with the input groups of the first to the second OR-HY, respectively, output of the comparison instruction of microinstructions connected to the first input of the first element And, the output of which is connected to the synchronization input of the first shift register, the output of the sign of the non-comparison of the register of microcommands is connected to the first input of the second And the output of which is connected to the synchronization input of the second shift register, the information inputs of the first and second shift registers are connected to the outputs of the first and second elements SH-NOT, respectively, the first output of the clock generator is connected to the clock input of the microinstruction register, the second clock output is connected with the second inputs of the first and second elements And, the outputs of the address field of the memory block and the output of the first element OR are connected to the information inputs of the register address input sync onizatsii coupled to an output of the third AND gate, the output address connected to the address input unit memory outputs floor upravle- NIN is connected to the data inputs of the register Microcom 0000 0001 0010 0100 1000 0001 0010 1000 1000 0 five about five 0 mand, a group of outputs of the code whose logical conditions are connected to a group of control inputs of a multiplexer whose output is connected to the first input of the third element AND, the output of the sign of the next address of the microcommand of the memory block is connected to the first input of the first OR element, the second input of which is connected to the output of the fourth And, the first input of which is connected to the output of the attribute of the memory block address modification, the high-order output of the second shift register is connected to the second input of the fourth And element and the first input the multiplexer input, the high-order output of the first shift register is connected to the second information input of the multiplexer, the control input of which is connected to the trigger output, the third information input of the multiplexer is connected to the output Equal to the comparison element and the fourth input of the analysis unit, the output of the analysis unit is connected to the first input of the second OR element, the output of which is connected to the zero input of the trigger, the second input of the second OR element is connected to the output of the end-of-microcontrols control, you od ayaliza feature which is connected to a fifth input of the analysis unit, a sixth input coupled to a third output clock pulse generator of the torus and to the second input of the third element I. Table 1 A B A B I 0100 1000 0000 0001 0010 0100 0000 0001 0010 0000. 0001 0001 001.0 II0100 1000 1000 1000 1000 1000 0100 0100 V0100 0010 0010 1000 1000 0100 0100 0100 0100 0010 0010 0010 0001 .0001 0000 0000 0000 0000 0001 0010 0100 1000 0000 0001 0100 0000 0001 A B A- in And in And in And in A. in And in And in  at A- in  at And in And in And in A b BUT; AT And in A b A b A b A b A b Continued table. I eleven eleven eleven eleven eleven 1 1 1 eleven eleven 1 1 1  eleven Table 2