SU473180A1 - Device for testing comparison circuits - Google Patents

Description

one

The invention relates to the field of automation and computer technology and can be used in the implementation of technical means of digital automation and digital computers.

Devices are known for testing comparison circuits, the contents of which are two binary counters, the bit outputs of which are connected to the inputs of the comparison circuit being tested, a trigger and an unequal element.

However, the known devices are complex, and the verification of the comparison schemes with their help is laborious.

The aim of the invention is to simplify the device and the verification process of comparison circuits.

This goal is achieved by the fact that in the proposed device the overflow outputs of binary counters are connected to the trigger inputs, one of the outputs of which and the output of the tested comparison circuit are connected to the inputs of the inequality element, the output of which is connected to the indicator input. The inputs of both binary counters are connected to the clock signal bus, and the input of one of them is connected to the input preset.

The block diagram of the device shown in the drawing.

The device contains binary counters 1,

2, trigger 3, an element of inequality 4 and indicator 5.

The device works as follows. On the beginning of the verification of the comparison circuit 6, the counters 1 and 2 are set to the zero position (the reset circuits are not shown in the drawing). Then, the number n is recorded in counter 2, and clock pulses are added to the input of both binary counters. The overflow of overflow of counter 2 into trigger 3 is written to one, and when the counter 1 is not filled, trigger 3 is set to zero. In the time interval after 1 mppul is full of counter 1 and before the pulse of the superfluid counter 2, the contents of counter 1 are less than the content of counter 2 (if the circuit is in good condition compared to 6, the signal “O” should be output). During the time interval after the pulse of the overflow of counter 2 and before the pulse of overflow of counter 1, the contents of counter 1 are larger than the contents of counter 2 (in a good condition of the circuit compared to 6, the signal "1" should be output). At specified intervals

trigger 3 is respectively in the "O and" 1 states. If an element of unequal 4 comes from trigger 3 and comparison circuit 6 with the same signals (or "O or" 1 through both inputs at the same time), then

at the output of the unequal element 4 there is a signal “O, at which the indicator 5 is off. In the case of a faulty state of the comparison circuit 6, the signals "O and" 1 are at the output of the signal at the times when the trigger 3 is in opposite states. As a result, signals "1" start appearing at the output of the inequality element 4, which include indicator 5 (the indicator can include a pulse expander on a one-shot or a trigger to turn on the indication after the first fault of the comparison circuit 6). Due to the fact that the contents of binary counters 1 and 2 are continuously changing, the verification of the comparison circuit 6 is carried out with different signals at its inputs, which increases the reliability of its control.

Subject invention

A device for checking comparison circuits containing two binary counters, outputs

the bits of which are connected to the inputs of the comparison circuit being tested, a trigger, an unequal element and an indicator, characterized in that, in order to simplify the device, there are binary overflow outputs in it

the counters are connected to the trigger inputs, one of the outputs of which and the output of the tested comparison circuit are connected to the inputs of the inequality element, the output of which is connected to the indicator input; moreover, the inputs of both binary counters are connected to the bus clock signals, and the input of one of them - with the input bus preset.