SU1338028A2 - Device for separating single n-pulse - Google Patents

Abstract

The invention can be used in digital computing and can improve the reliability of ycTpoiicTBa. The device contains a subtractive counter 1, triggers 2-4 and 16, elements 5 and 6 of the match, element NOT 7, a group of 12 elements HCKJTWMAbJDIEE W1H. The introduction of elements S1NI 13 and 15, the elements NOT 14 and the formation of new functional connections allow control of the entry of input information and indication of a failure. I il. (L with CvO oo 00 o y 00 MS)

Description

11338028

This invention relates to pulsed

technology, can be used in digital computing, in devices of automation and telemechanics for the selection of any n-th pulse from a pack or a continuous sequence of pulses and is an improvement of the author. No. 1001454.

The purpose of the invention is to increase the reliability of operation by monitoring the entry of input information and failure indication (failure).

The drawing shows an electrical functional circuit diagram of the device. I

The device contains subtraction

counter 1, first 2, second 3 and third 4 triggers, first 5 and second 6 elements of the match, first element 7 NOT, bus 8 of the control signal, bus 9 of the pulse train, output bus 10, bus 11 of the code, group 12 of the elements EXCLUSIVE STI , the first element 13 OR, the second element 14 is NOT, the second element 15 OR, the fourth trigger 16 and the bus 17 Failure, while the inverse output of the second trigger 3 is connected to the R input of the first trigger 2, the counting input of which is connected to the control signal bus 8 and the direct output is connected to the R-input of the third trigger 4 and the second in the house of the first element 1ta 5 matches the first input of which is connected to the output of element 7 NOT and the counting input of the detracting counter 1, and the output connected to the S input of the third trigger 4, the direct output of which is connected to the input of the resolution entry of the deducting counter code I, R input the second trigger 3, the counting input of which is connected to the output bus 10 and the output of the second coincidence element 6, the inputs of which are connected to the direct output of the first and inverse outputs of all other bits of the subtracting counter 1, to the output of the third trigger 4 and to the bus 9 of the pulse sequence, which is connected to the input of the element 7, NOT, the information inputs of the detracting counter 1 are connected to buses 11 of the code, and the first and second inputs of the group 12 of the EXCLUSIVE ILTIH elements are connected to the corresponding inputs and outputs of the detracting counter 1, and their outputs are connected to the inputs the first element 13 OR is the output of which through the second element 14 is NOT and is directly connected to co2

responsibly with the D inputs of the first 2 and fourth 16 flip-flops, the C input of the fourth flip-flop 16 is connected to the bus 8 of the control signal and the first input of the second element 15 OR, the second input of which is connected to the inverse output of the fourth flip-flop 16, H input and etc. my output of which is connected respectively with the output of the second element 16 OR and with the bus 17 Failure.

The device works as follows.

In the initial state on bus 8 there is no signal (zero level), bus 9 contains an input continuous pulse sequence that is inverted by element 7. At the direct outputs of the first 2, third 4 and fourth 16 flip-flops there are zero levels, at the outputs of elements 5 and 6 and on the inverse trigger output 3 — unit levels; on tires II, a binary code is set, for example, equal to (0101), which is also present on the outputs of counter I. In case of a mismatch (for example, due to a malfunction of the counter I or the device startup in see moment code) of the input code with the code at the output of counter 1 for one or several bits at the output of one or several elements of group 12, a single level occurs, coming through element 13 to the D input of the trigger 16 and through element 14 (already zero level) - on the D-input trigger 2. On the bus 10 there is a single level.

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With the arrival of the control signal

On the 8 vno bus, the Q-difference of the zero level per unit) trigger 2 does not work (there is a zero level at the D input) and the device does not start up. Thus, the issuance of incorrect information on the bus 1.0 Impossible. At the same time, the trigger 16 is triggered, at the direct output of which a single

The 0 level that arrives on bus 17 signals that no response will follow on request, since it is erroneous due to mismatch of the input and information entered into counter 1. After removing the control signal from the bus 8, the first input of the element 15 receives a zero level, which, together with the zero level from the output of the trigger 16, sets the latter to zero

five

a state in which the unit level is removed from the bus 17.

If the input bus code 11 matches the code at the output of counter 1, at the output of all elements of group 12 there is a zero level that goes through element 13 directly to the D input of the trigger 16 and in element 14, a unit level to the D input of the trigger 2. Incoming at the same time, the control signal on the slit 8. (on the difference from the zero level to the unit one) triggers trigger 2, the output of which is a unit level, which removes the trigger 4 setting at the R input and simultaneously enables the zero level of the input pulse sequences from bus 9 go through element 7 and element 5 to S-input of trigger 4, as a result of which a single level is established at its output, by which the blocking of trip-er 3, element 6 and counter 1 is released. Simultaneously with triggering of trigger 2, zero is confirmed the state of the trigger 16, while on the bus 17 is held zero level, indicating the absence of erroneous treatment. Counter 1 starts subtracting from the content equal to 0101. The subtraction is performed on a slice (difference from a unit level to zero) each is passed through the counting pulse input to counter 1, but since the input pulse passes through element 7, the difference is inverted and the triggering by counting the input occurs during a differential from a zero level to a single signal from the output of element 7. The subtraction continues until state 0001 remains in counter 1. During this time, subtracting counter 1 is calculated

There are four input pulses transmitted by 45 inputs of the first element OR, the output

via bus 9. The next fifth pulse is passed through element 6 to bus 10 by the zero level.

At the end of the fifth input pulse, the counter 1 is set to the zero state (0000). At the end of the selected pulse, a drop occurs from the zero level to a single on bus 10, which triggers 3. As a result, the zero level from its inverse output is set to H -in the trigger

0

0

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0

2 to the initial state. The zero level from the output of the trigger 2 blocks element 5 (a single level appears at its output) and sets the initial state to the R input of the trigger 4. The zero level from the output of trigger 4 blocks element 6, returns trigger 3 to the initial state by R input, and enters code 0101 from bus 11 to counter 1 and raises its counter input at the ramp entry input. The device returns to its original state.

When the next control signal is received, the operation cycle is repeated if the device is not self-blocking due to a mismatch of the input and information entered into subtracting counter 1. Meng is a binary code on Schinn 11, any nth pulse can be distinguished. Selection does not occur only in the case of device self-blocking or with code 0000, the range of the control signal duration is not limited, the minimum duration is determined by the response time of trigger 2.

Claims (1)

Invention Formula A device for the selection of a single p-th pulse auth.St. No. 1001454, which differs from the fact that, in order to ensure the reliability of work by controlling the input information, the first and second elements OR, the second element NOT, the fourth trigger, the Failure bus and the group of elements EXCLUSIVE OR, the first and second inputs of each of which are connected to the corresponding inputs and outputs of the subtractive counter, and the outputs to the corresponding through which the second element is NOT and is directly connected respectively to the D-inputs of the first trigger and the fourth trigger, the C-input of which is connected to the control signal bus and to the first input of the second OR element, the second input of which is connected to the inverse output of the fourth trigger, the R input and the direct output of connected. respectively, with the release of the second element of the Sh1I and bus Failure.