SU666645A1 - Error-checking binary counter - Google Patents

Description

(54) BINARY COUNTER WITH CONTROL OF ERRORS

The counting pulses are input to input 12, zeroing pulses to input 13, and polling pulses to input 14. Input 15 is designed for setting the zero of the control trigger. The output 16 is the output of the control trigger.

The polling pulses at input 14 (Fig. 2a) should be ahead of zeroing pulses at input 13 (Fig. 26), which, in turn, should be ahead of the counting pulses at input 12 (Fig. 2c).

The counting inputs of the D-flip-flops 2-4 are connected to the unit outputs of the corresponding bits of the binary counter 1, and the counting input of the D-flip-flop 5 is connected to the zero output of the last bit. The inputs of each of the elements OR 6-9 are connected to the zero output of the corresponding D-flip-flop and to the single outputs of the other D-flip-flops. The inputs of the element And 10 are connected to the outputs of the elements OR 6-9 and with the input of the polling pulses 14. The output of the elements 10 And connected to the input of the installation in the unit state of the control trigger 11. The input 13 is connected to the R inputs of all D-flip-flops signal is 1.

The principle of operation of the circuit is as follows.

The counter uses the property of D-flip-flops to go to one state (if there is a logical unit at the input) at the moment of influence on the counting input C of the difference from the level of logic zero to the level of the logical unit and set to its original state (for example, zero to input R) regardless of the presence of constant logical signals at inputs C and D. During normal operation of the counter, when a counting impulse arrives at input 12, only one trigger of the counter goes into one 1th state (or overflow of the counter, the last trigger goes into the zero state). Therefore, during normal operation of the counter, only one D-flip-flop (from D-flip-flops 2-5) goes into one state, the rest remain in the zero state. Since there is one OR element (from among the OR-6-9 elements) that is connected to the zero output of this D-TpKrrepa and the single outputs of the other D-flip-flops, at all inputs of this element OR there are logical zeros. The output also has a logical zero. Element AND 10, upon arrival of a polling pulse, does not generate a signal, and control trigger 11 remains in the zero state. If, when a counting pulse arrives at the input 12, no trigger of counter 1 goes into one state (or the last trigger does not go into zero), all D-triggers remain in the gull state, all elements of OR 6-9 produce a level logical unit. As a result, according to the impulse of the survey, the control trigger detects a failure (malfunction).

It is possible to randomly transfer (fail) any trigger of counter 1 (or one or several triggers of counter 1) to a single or zero state in the interval between the action at the input of 12 counting pulses. In the first case, this immediately leads to the transition of the corresponding D-flip-flop to a single state. In the second case, such a failure causes the subsequent trigger of the counter to go to the zero state, up to the trigger, which is already in the zero state, which goes into the single state. It also triggers the transition to the single state of the associated D-flip-flop.

Thus, in the event of such a counter in a single state, there is another (or more than one) D-flip-flop, besides the one that went into a single state when the last counting pulse arrived. This leads to the fact that all elements OR 6-9 produce a level of logical units. As a result, the control trigger detects a failure according to the polling pulse.

From this, it follows that the normal state of D-flip-flops 2-5 in the period between counting pulses, indicating that the counter is working correctly, is one in which one O-flip-flop is in a single state, the rest are in a zero state.

Claims (2)

All other conditions result in the appearance at the output of all elements of OR 6-9 a logical unit level, which is detected by the control trigger when a polling pulse arrives. Claims An error-controlled binary counter containing a n-bit counter on triggers and a control trigger, characterized in that, in order to increase the reliability of the control, n + 1 O-triggers, n + 1 elements OR, and element I are entered into it, moreover, the counting input of each D-flip-flop, except for n -I-1th, is connected to the single output of the corresponding digit of the counter, and the counting input of n + 1th Dtrigger is connected to the zero output of the n-th digit of the counter, the inputs of each element OR connected to zero output of the corresponding D-flip-flop and to one GOVERNMENTAL outputs other D-flip-flops, the outputs of OR elements are connected to the inputs of AND elements, IEs one input of which is connected to the input interrogation pulses, and an output connected to the input setting unit controlling the trigger condition. Sources of information taken into account during the examination: 1. USSR author's certificate No. 355746, H 03 K 21/34, 1972., 2. USSR author's certificate number 363215. H 03 K 21/34, 1972. but) 6} L.