SU433643A1 - - Google Patents

Description

(54) REVERSIBLE IMPULSE

one

The invention relates to the field of automation and computer technology and is not intended for automatic control and monitoring systems.

: Known reverse counter on the main author. St. No. 314313.: The proposed device is characterized in that, in order to increase reliability, an inverter is inputted into it, the input of which is connected to the output of the zero state allocation circuit of all bits, and the output to the input switches of input signals of the counting input subtraction.

The drawing shows a block diagram of the proposed device.

The pulse counter contains a logic circuit 1 and a reversible counter 2. Logic circuit 1 includes a decoder 3 connected to a reversible counter, a zero-state allocation circuit of all bits, input circuits 4 and 5 coincidence, trigger sign 6, output circuits 7-10 match, input switching keys, AND, "OR 2 and 13 inverter, input buses 14 and 15.

The device works as follows. At the initial moment of time (account triggers: Chick in the zero state), the resolution potential is applied to the inputs of the constellation schemes 4 and 5 through gaps $ 3. When entering on | the input bus 14 of a sequence of m pulses, the first of them is fed to the inputs of circuits 7 and 9, and also through scheme 4; matches to the trigger input of sign 6.

The first impulse arrives at the matching schemes 7 and 9 before the matching scheme 4 and the trigger 6 of the signal work, therefore it is open; We look at the initial state of the trigger. Suppose that the trigger of sign 6 is in the state when the inhibition potential arrives at the output — coincidence circuit 7 — and the output potential of the resolution 9 arrives at the output coincidence circuit 9. Then the first impulse will pass through the coincidence circuit 7 only when the trigger 6 is triggered. If the trigger 6 is in the state when the coincidence circuit 7, the OR 12 circuit and enters the reversing counter 2-addition. The trigger state of sign 6 does not change.; Through the coincidence circuit 9, the first pulse does not pass in any state of the 6 sign trigger, since the inhibitory potential from the output of inverter P is fed to its input. After the eras-:; sign trigger b jumps to the input;

On the reversible counter 2, it is recorded 1. In this case, from the decoder 3, the inhibit potential is fed to the matching circuits 4 and 5, and the matching circuits 8 and 9 from the inverter 11 have a resolution resolution. The second, third and that "further pulses of the number t pass through the circuit of the input bus 14, the matching circuit 7, the circuit OR 12, the input of the reversible counter 2 for addition. At the end of the count, the number m is written to the reversible counter 2. If then the pulses start to enter the input bus 15 from the pulse sequence n, and the pulse arrives on the input bus 14, the first, second and so on pulses pass along the circuit of the input bus 15, a matching circuit 8, an OR 13 circuit, a reversible counter 2 input for subtraction. Pulse does not pass through circuit 10, since the inhibitory potential from the output of the trigger sign 6 is fed to its input. Thus, the number n is subtracted from the number m.

At the point in time when n t. On reversible counter 2 is set the number

OO, from the output of the decoder 3 to the circuit 4

and 5 coincidence, the resolution potential is applied, and the inhibit potential from inverter P. is fed to coincidence circuit 8. If the supply of pulses to the input bus 15 continues, then (n- | -1) -th 1 pulley goes to the inputs of circuits 8 and 10 c6vg1a; , but their 11 does not pass, since the prohibiting potential from the inverter AND ,:, 8 enters the circuit 8 of coincidence and the circuit 10 coincides - the prohibiting potential from the output of the sign trigger 6. And only; after the trigger of the sign triggers via scheme-1, th 5 matches (l + 1) -th pulse through the coincidence circuit 10, the scheme "OR 12 is fed to the input of the reversible counter 2 for addition. / Through the circuit 8 coincidences (n - {- 1) - Your impulse and subsequent ones do not pass, because

its input is supplied by the inhibitory potential of inverter 11, and after the trigger of sign b triggers, the inhibitory potential from its output to another input of the circuit. On the reverse counter 2 is recorded 1. The second, third, and so on pulses of the sequence n

| pass through the circuit, the input bus 15, the coincidence circuit 10, the circuit OR 12, the input of the reversing counter 2 for addition.

Subject invention

Reversing pulse counter on aut. St. No. 314313, differing by; that, in order to increase reliability, an inverter is introduced into it, the input of which is connected to the output of the zero state allocation circuit of all bits, and the output to the inputs of switching keys of input signals at the subtracting input of the counting scale.