SU1640822A1 - Frequency-to-code converter - Google Patents

Abstract

The invention relates to a measuring technique and can be applied in measuring systems with frequency sensors. The purpose of the invention allows to simplify a converter comprising a counter 1, a register 2, a memory, an input source 3, a counter 4, a key 5 and a reference frequency generator 7. the elimination of the second register and the three logical elements and the introduction of the two elements AND-NOT 6, 8, as well as new connections between the elements of the circuit 1 or 0

Description

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The invention relates to a measuring technique and can be applied in measuring systems with frequency sensors.

The aim of the invention is to simplify the device.

The drawing shows the functional diagram of the frequency converter in the code o

The frequency converter in the code contains a pulse counter 1, a register 2, an input signal source 3, a pulse counter 4, a key 5, an AND-HE element 6, a reference frequency generator 7, an AND-80 element

The frequency converter in the code works as follows

The voltage frequency is measured by counting the number of pulses of the reference frequency during each period of the input signal, while register 2 stores the result code and its outputs are outputs of the device, Counter 1 performs the count of the number of pulses of the reference frequency, and at the time of arrival of the next pulse from the output of source 3, t „e„ with a positive signal front, the code from the output of counter 1 is entered into register 2 „. From this moment of time the level of the logical unit, which enters the input of pre-recording, the counter 4, permits the last count reference clock pulses arriving at the input account alternation switch 5 "

When the logical element 1 signal is present at the inputs of the NAND 8 element, the logical signal O arrives at the preliminary recording input of counter 1, the code from the outputs of counter 4 is rewritten into counter 1 s. This occurs when the output signals of counter 4 are D1 .1 and 1) 2 1 , i.e., after the arrival of two pulses of the reference frequency, taking into account the fact that counter 4 was previously set to the state D1 - 1 and D2 00

The third reference frequency pulse sets a new code at the outputs of counter 4, and the logical 1 signal from the output of the NAND element 8 enables the counting of pulses to counter 1 “When the fourth reference frequency pulse arrives, counter 1 continues counting, starting with code D1 1 and D2 1, Te0e0 from the number 3m, which corresponds to the number of pulses received

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from the output of the generator 7, starting from the moment of the leading edge of the signal from the output of the source 3 "

When the inputs of the AND-NOT 6 element are logical 1 signals, and this happens when 1) 1 1 and D2 1, the logical 0 signal sent to the control input of key 5 prevents the reference frequency pulses from passing to counter 4, which causes his stop ,,

When the measured signal level changes from a logical 1 to a logical VO, counter 4 is preset to the state in which it is before the arrival of the leading edge of the signal from the output of source 3, and counter 1 continues counting, since the output of the AND-NOT element 8 will be a logical signal

At the moment when the leading edge of the measured signal arrives, the code from the outputs of counter 1 is again rewritten into register 2, and counter 4 starts counting the pulses of the reference frequency from state D1 1, i.e., e0, the measurement process repeats.

The monitored signal must comply with the operating parameters of the digital logic, which can be achieved with the help of an input signal shaper, a component of the input source, or a special design of the source 30

Claims (1)

Invention Formula A frequency converter into a code containing an input source, a serially connected reference frequency generator, a key and a first pulse counter, the register whose outputs are the output bus and the information inputs are connected to the corresponding outputs of the second counter pulses. different By the fact that, for the sake of simplicity, two NAND elements are introduced, the outputs of which are connected to the control input of the key and the preset input of the second pulse counter, respectively, the counting input of the second pulse counter is connected to the output of the reference frequency generator, and the information inputs are connected to the corresponding -; current outputs of the first counter 516408226 pulses, information inputs of the input source, output which, besides the first one, unites the first bit of the first counter, they are connected to the logical bus. Nu-pulses are connected to the first inputs l, and the first information input is the first and second elements AND-NOT, to the bus of the logical unit, the input outputs of the second and third bits of the preset of the first counter of them-to the second inputs of the second and pulses combined with the input of the input-first elements AND-NOT corresponding register and connected to the output.