SU790231A1 - Pulse train monitoring device - Google Patents

Description

one

This invention relates to pulse train control devices containing the same number of pulses.

A device for monitoring pulse sequences is known, in which the control of pulse sequences is performed by counting the number of pulses.

However, this device is very complicated.

The closest in technical essence is a device in which four tires of pulse sequences are contained, which 15 are fed to the inputs of an OR gate, to the output of which a trigger cell is connected.

The input signals from the trigger are sent to the two-input logic element 20, the other input receives pulses from one of three controlled pulse sequences, the pulses of which do not coincide with the output signals of the trigger, the other output of the trigger cell And to the other the input of this element is the output of a logical element OR, the inputs of which are impulses of two 30

of other controlled sequences, parcel, the same four controlled pulse sequences are pairwise inputted to logical elements AND, outputs from these elements are assembled into OR elements, the output from which is inputted to the input of an OR element, and the other input is outputted from AND element 2.

However, this device does not allow for the control of pulsed sequences arriving at different clock frequencies and pulse sequences whose pulses are automatically located at a controlled time interval, which is a drawback of the device.

The purpose of the invention is to expand the functionality of the device.

This goal is achieved by the fact that a device containing a logical & element, two shift registers and a decoder, has two delay elements and two switching elements, and the outputs of the shift registers are connected to the inputs of the decoder and to the first two inputs of the AND element , and the outputs of the decoder each through its delay element connected to

the primary inputs of the first and second commuting elements, the inputs of which are interconnected.

The drawing shows the functional diagram of the device.

The device contains busses 1 and 2 of control pulse sequences, shift registers 3 and 4, decoder 5, delay elements b and 7, switching elements 8 and 9, elements 10, interrogation bus 11, output bus 12, tires 13, 14 and 15 clock frequencies, bus 16 and 17 control signals.

The device works as follows. . .

The device operates in the recording and control modes. In the recording mode, control signals are sent to buses 15, 16 and 17, as a result of which the signals of buses 13 and 14 of clock frequencies, regardless of the signals from the outputs of the delay elements 6 and 7, go to shift registers 3 and 4. Since the signals from the buses 13 and 14 of the clock frequencies are separate, from the registers 3 and 4 of the shift can be entered the pulse sequence, arriving with a different clock frequency.

In the pulse control mode, the control signals for the control bus 15 16, 17 are not supplied, as a result of which the clock bus 15 is switched to the shift registers 3 and 4. In this case, the clock signal depends on the signals from the outputs of elements 6 and 7 of the delay.

The principle of control lies in the synchronous output from the registers 3 and 4 of the shift of the same signals. If there are 3 and 4 shift registers in the last bits.

If the last bits of registers 3 and 4 have different signal shifts, the signals of only one register are shifted depending on the combination of different signals. This process will continue until the outputs of the registers 3 and 4 shift the signal of the same name. The process then repeats. Thus, if the pulse sequences contain the same number of monitored signals, before the arrival of the signal, the polling from the bus 11 must be derived from the registers 3 and 4 of the shift for the last bits of which there will be signals of the same name. In case of inequality of the number of monitored signals in the pulse sequences, the last bits of registers 3 and 4 of the shift will be the opposite signals, indicated

the inequality is revealed by the element AND 10

upon arrival of a signal, a survey from bus 11. The present invention allows to control pulse sequences, determining the correctness of performing various logical operations in which various permutations of pulse signals are made while maintaining the number of pulses. The use of the proposed device for controlling impulse sequences will allow. To increase the equipment readiness, to eliminate the possibility of false effects on other devices or objects, to increase

equipment serviceability.

Claims (2)

Invention Formula Q A device controlling pulse sequences containing a logical element AND, a left shift register and a decoder, which is such that, in order to expand the functionality of the device, two delay elements and two switching elements are introduced into it, and the outputs the shift registers are connected to the inputs of the decoder and the first two inputs of the element I, and the outputs of the decoder each through its delay element connected to the first inputs of the first and second switching elements the second inputs of which are connected between with myself. Sources of information taken into account in the examination i; Patent of Germany 2.038.211, cl. H 03 K 5/19. 2. USSR author's certificate No. 515271, cl. H 03 K 5/19, 1974. 0 about -0 (5