SU1649577A1 - Multichannel pulse counter - Google Patents

Abstract

The invention relates to computing and instrumentation and can be used to count and indicate the number of pulses produced by several sensors. The purpose of the invention is to increase the reliability of operation. The multichannel counting device contains inputs 8-10, triggers 2 receiving information, triggers 1 issuing information, elements AND-NOT 3, element OR 4, inverter 4 and indicator 5. 2 Il.

Description

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FIG. one

The invention relates to automation, computing and measurement technology and can be used to count and indicate the number of pulses from several simultaneously operating sensors.

The purpose of the invention is to increase the reliability of operation.

FIG. 1 shows a structural electrical circuit of a three-channel pulse counter, FIG. 2 - diagrams of his work.

The three-channel pulse counter contains the triggers 1, and 2, the elements AND-NO 3, the element OR 4, the indicator 5, the element NOT 6 and the inputs 7-10.

The output of the element, OR 4 is connected to the indicator 5, the inputs 8-10 of the counting channel are connected to the C-inputs of the corresponding information receiving triggers 2. The direct outputs of the information receiving flip-flops 2 are connected to the D-inputs of the corresponding information-flip-flops 1. Direct Trigger Outputs

1 output information is connected to the first inputs of the corresponding elements AND-NOT 3. The output of each element AND-NOT connected to the R-input of the trigger 1 receive information of this channel and with the corresponding inverse input of the element OR 4.

Input 7 of the polling signal is connected to the C-input of the trigger 1 for issuing information and through the element NOT 6 to the second input of the element AND-NOT 3 of the last channel. The second inputs of the elements AND-NOT all channels are combined. The subsequent inputs of each of the elements AND-NOT are connected respectively to the inverse outputs of the triggers 2 receptions infbromatii all previous channels. D-inputs trigger

2 receiving information of all channels are connected to the bus 11 of a single logical signal.

The counter works as follows.

On the leading edge of the pulses arriving at inputs 8-10 (Fig. 26), triggers 2 are set to one (Fig. 2c). According to the front Auront of the first polling pulse at input 7 (Fig. 2a), triggers 1 are set to 1 in the presence of a positive potential at the direct output of the corresponding trigger 2 (Fig. 2d). Elements AND 3 NOT open on the first inputs with a single signal of the corresponding triggers 1.

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When the first positive pulse arrives from the output of the NOT 6 element to the second input of the NAND 3 element of the first channel, a negative pulse is formed at the output of the last equal to the polling pulse duration (Fig. 2e), which through the OR 4 element enters the pulse counting indicator 5 ( Fig. 2h). At the same time, the impulse from the output of the NAND 3 element of the first channel arrives at the R input of the trigger 2 of the same channel, setting it to the zero state (Fig. 2c). A single signal from the inverse output of the trigger 2 opens on the third inputs the elements AND-HE 3 of the second IR of the third channel. On the leading edge of the second polling pulse at the input 7, the trigger 1 of the first channel is set to zero (initial) state (Fig. 2d).

Upon receipt of the next positive impulse from the output of the NOT 6 element to the second input of the IS-NOT 3 element of the second channel, a negative impulse is formed at the output of the last (FIG. 2e), which through the OR 4 element enters the pulse counting indicator 5 (Fig. 2h). At the same time, the pulse from the output of the IS-NE element 3 of the second channel arrives at the R input of the trigger 2 of the same channel, setting it to the zero state (Fig. 2c). A single signal from the inverse output of flip-flop 2 opens on the fourth input of the NAND element 3 of the third channel. On the leading edge of the third interrogation pulse at the input 7, the trigger 1 of the second channel is set to zero (initial) state (Fig. 2d).

When the next pulse arrives from the output of the NOT 6 element to the second input of the IS-3 element of the third channel, a negative pulse is formed at the output of the latter (FIG. 2g), which through the OR 4 element enters the pulse counting indicator 5 (Fig. 2h). At the same time, the pulse from the output of the third channel IS-3 element enters the R input of the trigger 2 of the same channel, setting it to the zero (initial) state (Fig. 2c).

Thus, the pulses to be counted arriving simultaneously to all the inputs 8-10 of the multi-channel counter are counted by the indicator 5 in series with the polling frequency.

Claims (1)

Invention Formula A multichannel pulse counter containing an OR element, an output connected to an indicator, and N counting channels, each of which consists of an information receive trigger, an information trigger, and an NAND element, the counting channel input connected to the C input of the information receive trigger, direct the output of which is connected to the D-input of the information output trigger, the direct output of which is connected to the first input of the NAND element, the output of which is connected to the R-input of the information receiving trigger of this channel and from the same; i JTLLJLJTLJ LJ f 48j t & w Uz 4V five inverse of the input element OR, while the input of the interrogation signal is connected to the C input of the trigger for issuing information and through the element NOT to the second input of the AND-N element of the last channel, characterized in that, in order to increase the reliability of the operation, all channels are connected, their subsequent inputs are connected respectively to the inverse outputs of the information receiving triggers of all previous channels and the D inputs of the information receiving triggers of all channels connected to the single logic signal bus. Lj U Lj giit