SU1679626A1 - Counting unit - Google Patents

Description

The invention relates to devices, pulse technology and can be used in automatic control systems

control, in computing devices and digital measuring equipment to perform the functions of counting conditional states; The purpose of the invention is to expand the functionality by providing the count of given code combinations. The counting device contains counter 1, ϋ-flip-flop 2, digital comparator 3, elements AND 5 and 6, elements OR 7 and 8, driver 9, additional counter 10 and element 11 of the permanent memory storing the sequence of specified code states. The device provides a comparison of the code sequences at the input 4 with the given one, and their counting, and if they do not match, forms a signal at the output 14. 1 Il.

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The invention relates to devices of pulse technology and can be used in automatic control systems, control, computing devices and digital measuring equipment to perform the functions of counting conditional states.

The aim of the invention is to enhance the functionality by ensuring the counting of given code combinations.

The drawing shows a structural diagram of the counting device. ,

The counting device contains a counter 1, β-trigger 2, digital comparator 3, the first group of inputs of which is connected to the group of information inputs 4, two elements AND 5 and 6, two elements OR 7 and 8, driver 9, additional counter 10 and element 11 constant - memory of storing the sequence of given code states, the clock input 12 of the device is connected to the input "equal to" digital comparator 3, with the inverse dynamic clock input β-trigger 2 and the first input of the first element And 5. whose second input is connected to the direct output β of the trigger 2 and the first input of the second element AND 6, the output of which is connected to the first input of the first element OR 7, the output of which is connected to the reset input of the β flip-flop 2, the β input of which is connected to the bus 13 of a single logical signal, the output of the first element And 5 is controlling output 14 of the device and connected to the first input of the second element OR 8, the output of which is connected to the reset input of the counter 1, the direct dynamic counting input of which is connected to the output "equal to" digital comparator 3, which is connected to the second input of the second element And 6, the second a group of inputs of the digital comparator 3 is connected to the outputs of the element 11 of permanent memory, the auxiliary output of which is connected to the input of the former 9 and the clock input of the additional counter 10, whose information inputs are the output 15 of the code sequence number code, the output of the former 9 is connected to the second input of the second element OR 8, and the outputs of counter 1 are connected to the address inputs of the element 11 of permanent memory, and the third input of the second element OR 8 ′ is connected to the reset bus 16 of the device, which is connected to By resetting the additional counter 10.

The device works as follows.

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In the element 11 of the memory is entered before the start of the specified code combination. If this code combination is constant, then this element can be implemented as a masked ROM or a ROM with burning. If it can sometimes change, it is advisable to implement it in the form of a chip with ultraviolet or electric erasure. You can also use RAM chips as this element, given that the information in it does not change during the operation.

The peculiarity of the sequence of codes listed in element 11 is that a single logical signal is generated at the additional output only for the last of the codes in this sequence.

Before starting the signal on the bus 16, the device is set to its original state, i.e. counters 1, 10 and trigger 2 are reset to zero. The inputs 4 receive a sequence of input codes, and the input 12 - the accompanying sequence of clock (clock) pulses. When the codes at the comparator input coincide and if there is an inverse clock (synchronizing) pulse, a signal is generated at the comparator output, which is considered to be counter G. At the same time trigger 2 switches to one state upon receipt of the clock signal, and if the codes coincide with a certain delay determined by And 6 elements and OR 7, this trigger returns to the zero state. The code at the output of counter 1 is changed, and at the output of memory element 11, the following code is generated from the specified pulse sequence. After that, the device waits for the arrival of this code at the inputs 4. After the specified code sequence is completed, a signal is generated at the output, which starts the shaper 9 and is counted by the counter 10. The latter ensures the count of the number of code sequences received at the input.

If at some time the code at inputs 4 does not coincide with that specified at the output of element 11, trigger 2 is not reset to the zero state, and after the clock pulse ends, output 14 receives a single signal indicating a violation in the code sequence, but; stepping on the entrance. This signal can be used by external devices to register a violation in the input pulse sequence. This signal also goes to the reset 1 inputs of the counter,

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setting it to the zero state, which ensures further synchronization of the device operation with the input sequence, i.e. the device expects the appearance of the first of the codes in a given pulse sequence.

The device provides control of the input code sequence, synchronization with it and counting both the number of shoes in it, and the number of code sequences, and can be used in software-logic control devices, instrumentation and computing equipment for counting and monitoring signals on buses.

Claims (1)

Claim A counting device containing a counter, an O-flip-flop, a digital comparator 20, the first group of inputs of which is connected to a group of information inputs, characterized in that, in order to expand its functionality, by ensuring the count of 25 given sequences of code combinations, Two AND elements, two OR elements, a driver, an additional counter, and a permanent memory element for storing a sequence of specified code states, are introduced. the device input is connected to the input "is ¹ 'of the digital comparator, with the inverse dynamic input of the ϋ-flip-flop and with the first input of the first element And, the second input of which is connected to the direct output of the O-trigger and the first input of the second element And whose output is connected to the first the input of the first OR element, the output of which is connected to the reset input of the три-flip-flop 10, the input of which is connected to the single logic signal bus, the output of the first element AND is the control output of the device and connected to the first input of the second element OR, the output of the second element OR is connected to the reset input of the counter, the direct dynamic counting input of which is connected to the output "equal" to the digital comparator, which is connected to the second input of the second element And, the second group of inputs of the digital comparator is connected to the outputs of the permanent memory element whose additional output is connected with the input of the driver and with the clock input of the additional counter, whose information outputs are the output of the code of the number of cbdov sequences, the output of the driver is connected to the second the second input of the second OR element, and the counter outputs are connected to the 3θ address inputs of the permanent memory element.