SU447711A1 - Device for decoding a pulse code - Google Patents

Description

one

The invention relates to the field of automation and computer technology and can be used in telemechanics devices for analyzing the indication of messages, as well as in a sequence of operations controlled by a program with a digital computer.

There are known devices for a coding chip number pulse code containing a counter, the outputs of which are connected to the inputs of the decoder and the comparison circuit, a time delay circuit and a register, the inputs of which are connected to the program code buses, and the outputs of the register are connected to the inputs of the comparison circuit, control triggers, the single input of which is connected one of the output of the reset circuit, the other output of which is connected to the installation input of the counter, the zero output of the control trigger is connected to the input of the reset circuit, the OR circuit, the coincidence circuit and inv erter

However, the presence in such a device specifying a push-pull circuit for recording information into the counter of its speed-response.

The aim of the invention is to increase the speed of the decoding device of the pulse number code.

This is achieved by the fact that in it the control trigger zero input and the read input of the comparison circuit are connected via a time delay circuit to a single control trigger output connected to the first input of the fallout circuit, the device input bus is connected to the auxiliary input of the reset circuit and through the inverter to the second input a coincidence circuit, the output of which is connected via the OR circuit to the input of the counter, the overflow output of the latter is connected to another input of the OR circuit, the output of the comparison circuit is connected to the input of the qpa code.

The drawing shows a functional diagram of the proposed device.

The device contains a counter 1, the outputs of which are connected to the inputs of the decoder 2 and the comparison circuit 3, the time delay circuit 4 and the register 5, the inputs of which are connected to the U-buses of the program code, and the outputs of the register 5 connected to the inputs of the comparison circuit 3, control trigger 6 , the single input 7 of which is connected to one of the outputs of the reset circuit 8, the other output of which is connected to the installation input of the counter 1, the zero output of the control trigger 6 is connected to another input of the reset circuit 8, the OR circuit 9, the coincidence circuit 10 and the inverter 11. zero in d 12 control trigger 6 and readout input 13 of the comparison circuit 3 are connected via a time delay circuit 4 to a single output 14 of a control trigger 6 connected to the first input 15 of the coincidence circuit 10, the input bus 16 of the device is connected to the auxiliary input 17 of the reset circuit 8 and through the inverter 11 - with the second input of the coincidence circuit 1O, the output of which through the OR circuit 9 is connected to the input 18 s: of the clock 1, the overflow output 19 of the latter is connected to the input of the circuit OR 9, the output of the comparison circuit 3 is connected to the input 20 of the decoder 2. The device erzhit also reset bus 21 ft-bus and the output signals of the apparatus. The device operates as follows. In the initial state, the circuit is established by a low potential impulse, which goes along the fault bus 21. At the same time, at the output of the inverter 11 there is a high potential level, on the input buses of the fn-discharge code of the program and on the input bus 16 of the device there are low potential levels. At the end of the reset pulse, at the outputs of counter 1, at the ft outputs of the decoder 2, at output 14 of trigger 6, at input 12 of trigger 6 and at input 13 of comparison circuit 3, low potential is set at the output of reset circuit 8 and output of coincidence 10 and the output of the circuit OR 9 and the output 19 of the counter 1 is a high potential. .. Before incoming signals on the input bus 16 to the fft-discharge bus of the program code, a code corresponding to the pulse-shaped input code is received, and the time delay 4 is tuned accordingly. At the time the first input pulse arrives at the leading edge from one output of the circuit reset, an additional signal is sent to the installation of counter 1 in the initial COCTOS, and from the additional input to input 7 of trigger 6, a low potential about which trigger 6 is triggered, at the input of which a high potential is set l, and on the opposite - low potential. In this case, the potential from output 14 of trigger 3 triggers time delay circuit 4. On the falling edge of the input signal, reset circuit 8 finishes generating a signal. Resetting counter 1 to its initial state and holding it in this state for the entire time the circuit has been running: temporary; delays 4 are low from the zero arm of the trigger 6. In this case, through the inverter 11, the coincidence circuit 10 and the OR circuit 9, the leading edge of the first pulse of the pulse code enters the input of the counter 1. At the subsequent moments of the arrival of successive input signals via bus 16, on their leading edge, the reset circuit 8 and trigger 6 do not change their state; on the falling edge, the total number of pulse code is written to counter 1. Upon receipt of the expected number-pulse code and comparison with the programmed one stored in the regis-memory of memory 5, the comparison circuit 3 will be satisfied. At the time the time delay 4 triggers a low potential from its output, trigger 6 is set to input 12 to the original state and polling is conducted at input 13 of comparison circuit 3, from the output of which a readout signal is generated at input 2O of decipheror 2. At the same time, a signal corresponding to the input pulse code will appear on the corresponding one of the ft outputs. y, and the coincidence circuit of Input 15 and the scheme OR 9 will be set to the original one. condition. In subsequent m-r analyzes of the corresponding number-pulse codes, the device circuit is reset automatically by the leading edge of the input signal coming through bus 16. In the case of a distorted number-pulse code, the comparison circuit 3 does not work, and the interrogation signal at input 13 (from the time delay circuit 4) no read signal is generated at input 20 of decoder 2 and, accordingly, no output signal appears on the M-outputs of the device. When counter 1 is overflowed from output 19, the low potential disconnects the OR 9 circuit, prohibiting the input of the input signal through the bus 16. Thus, the proposed device providing recording of information to the counter on the falling edge of the input signal has an increased speed on the counting input along with