SU444177A1 - Device for recording random pulses - Google Patents

Description

(54) DEVICE FOR REGISTRATION OF RANDOM PULSES

I The invention relates to the field of automation and computer technology and can be used in systems for recording randomly arriving signals for outputting information from recording

counters in memory units, for example, in systems for registering failures in tests for reliability of electronic circuits, in analyzers of nuclear particles.

There are known devices for registering random pulses, which contain a counter with information transfer circuit and circuit.

for separating the polling pulses from the input pulses.

To eliminate losses of counted pulses at the time of arrival of the polling pulses, in known devices the time interval between the rear front of the one-vibrator, which performs: the function of delay for the time of the polling pulses, and the next input pulse must be no less than the minimum admissible period of arrival of input pulses

. pulses, which leads to a decrease in the speed of the device.

The aim of the invention is to improve the speed of the random pulse recorder.

This is achieved by introducing triggers, delay circuits, OR circuits, BAN circuit and valves, the recording input of the device through the first and second delay circuits connected in series to the input of the BAN circuit, the connection point of the delay circuits connected to the counter input of the counter, and the outputs of the first delay circuit through the first OR circuit are connected to the single input of the first trigger and the prohibiting input of the PROHIBITION circuit, the output of which is connected to the zero input of the first trigger and the pulse input of the first wave the ethyl, the potential input of which is connected to the single output of the second trigger, the single input of the second trigger and the pulse input of the second valve, the potential input of which is connected to the zero output of the first trigger, are connected to the control input of the device, the outputs of the valves I are connected to the corresponding inputs of the second OR circuit, the output of which is connected to the control inputs of the information transfer circuit and the counter, to the input of the third delay circuit, the output of which is connected to the zero input of the second trigger. Due to this, a delay of not interrogation pulses but of interrogation pulses is provided, as a result of which the pulses can follow with any frequency limited only by the speed of the counter itself and the output of information from the counter that does not depend on the time. The drawing shows the scheme of the proposed device. A device for registering random pulses contains a counter 1, a circuit for transmitting information 2, a memory block delay circuit 4, a registering input 5 of the device, an OR circuit 6, a trigger 7, a BAN 8 circuit, a delay circuit 9, a valve 10, an OR circuit 11, a valve 12, device control input 13, trigger 1. bxeivfy delay 15. The device works as follows. The recorded pulses are fed to the registering input 5 of the devices, from where, via the delay 4, they are fed to counter 1, which accumulates information at the frequency of the input pulses. Periodically, according to the signal supplied to the control input 13 of the devices, the contents of the counter are transferred to the storage unit 3 via the transmission circuit 2, and the counter is reset to the initial zero state. The omissions of the recorded pulses are possible if these pulses arrive at the input of the counter at the moments of the output of the information from it. To eliminate such errors, the control information output signal is delayed until such time as the time interval between the two with the first pulses or groups of pulses is sufficient for all operations on the output of information from the counter. The delay duration is defined by the parameters of the delay circuit 4. Suppose that the output control signal is jammed at the device input 13. This signal translates trigger 14 into a single state and, through valve 12, checks the status of trigger 7, if simultaneously with the input signal 13 or earlier than it by one or more time. several tacts on the yokor, 5 will receive one recorded pulse, then it switches the trigger 7 to the state I through the scheme OR 6 in each of the, prohibiting the possible return of the trigger to the state O using the BANNER scheme 8. As a result, there is no From the counter until the last pulse, extracted from the delay 4, passes through the serial connection of the delay 9, the open BAN 8, the open valve 10 and the OR 11 to the control input of the information transfer circuit 2. If input signal 13, the time period corresponding to the absence of recorded pulses is sufficient for outputting information, then the trigger 7 is in the O state, which allows the control signal through the open valve 12 to transfer the contents of the counter 1 to the storage unit 3 without any delay. At the end of the output of the control signal, having passed the delay circuit 15, the trigger 14 returns to the initial state. The device is ready for a new work cycle. Shadow Image Object A device for registering random pulses, containing a counter, the output of which is connected to the input of a storage unit through an information transfer circuit, characterized in that, in order to improve speed, triggers are introduced into it, delay circuits, OR circuits, BAN circuit and gates, the registering input of the device through the first and second delay circuits connected in series are connected to the input of the BANCH circuit, the connection point of the delay circuits is connected to the counting input of the counter, the input and outputs of the first c The delays are connected through the first OR circuit to the single input of the first trigger and the prohibiting input of the BREED scheme whose output is connected to the zero input of the first i trigger and the pulse input of the first valve, the potential input of which is connected to the single output of the second trigger, the single input of the second trigger and the pulse input of the second valve, the potential input of which is connected to the zero output of the first trigger, is connected & ny to the control input of the device, the valve outputs are connected to the corresponding inputs of the second of the OR circuit, the output of which is connected to the control inputs of the information transfer circuit and the counter, to the input of the third circuit of the delay, the output of which is connected to the zero input of the second flip-flop.