SU1554153A1 - Device for majority selection of asynchronous signals - Google Patents

Abstract

The invention relates to automation and computing and can be used in the construction of information and control systems of increased reliability. The aim of the invention is to expand the field of application of a code parcel device represented as a binary code with accompanying clock pulses, and the time of desynchronization of code parcels arriving at different inputs of the device is not limited. This task is solved by introducing into the device three input shift registers and three buffer registers, three decoders, three binary counters, and a third And element with corresponding links. 1 hp f-ly, 2 ill.

Description

The invention relates to automation and computing, and the set can be used in the construction of information and control systems of increased reliability.

The purpose of the invention is to expand the field of application by receiving and processing asynchronous code packets.

Figures 1, 2 illustrate a device for the majority selection of asynchronous signals.

The device for the majority choice of asynchronous signals contains input shift registers 1-3, binary counters 4-6, decoders 7-9, triggers of the first 10-12 and second 13-15 groups, elements 16-18, buffer registers 19-21, the first and the second majority elements 22, 23,

master oscillator 24 and distributor 25, informational and gating inputs of the device 26-31, informational 32-35 and strobing 36 outputs of the device.

The device for the majority selection of asynchronous signals operates as follows.

Before the start of operation, a reset signal (the reset circuit is not shown in Fig. 1) the device is reset.

A code package arriving at input 26 is transmitted to input shift register 1 by the accompanying clock pulses arriving at input 27 in bits, while binary counter 4 simultaneously counts the number of code send bits entered into the device.

SP

ate

4b

cl

with

When entering 4 bits at the output of the decoder 7 is set to 1, which is fed to the input of the trigger 13. But the falling edge of the frequency coming from the master oscillator 24, the trigger 13 is set to one and 1, appearing at the output of the trigger 13, generates a signal zeroing at the output of AND 16, on the front of which the information from input register 1 is transferred to the buffer register 19, and the binary counter 4 is zeroed.

Through the clock frequency of the master oscillator 24 1 from the output of the trigger 13 is recorded in the trigger 10, the output signal of which is fed to the input of the first major element 22, and the signal from the inverse output is fed to the input of the AND 16 element, which prohibits the formation of the zero signal.

After the desync time, the code parcel arrives at input 28, accompanied by clock pulses input to input 29, which is written to input register 2, and after the zero signal appears at the input of the And 17 element, is written to the buffer register 20. And the trigger output signal 11 enters the second input of the first major element 22. At the output of the first major element 22, a unit appears at the input of the pulse distributor 25, which is detected by the signal at the output of the pulse distributor 25, which is The gating output of the device resets the flip-flops 10-15, and information from the output to the majority element 23 can be used for further processing.

The maximum desynchronization time of the code sendings sent to different inputs 28–33 of the device is determined by the number of bits of the input buffer registers and the number of bits of the pulse distributor tpac nT- (R / f, r- 1), where T is the period of similar pulses

devices; fir - oscillator frequency

,

n is the number of bits of the input register (buffer register);

The number of bits of the pulse distributor.

Jq

15 2

25 Q

but}

35

45

50

B5

A necessary condition for the operation of this device is that two periods of the frequency of the master oscillator must be less than the duration of the input pulse.

Claims (2)

1. A device for the majority selection of asynchronous signals, containing the first group of three triggers, the outputs of which are connected to the corresponding inputs of the first major signal. the tare element, the second group of three triggers, the second major element, the pulse distributor, the master oscillator and the first and second elements AND, differing from the fact that, in order to expand the field of application, the first - third input shift registers are additionally introduced, three the decoder, three binary counters, three buffer registers and the third element And, the first, second and third information and gate inputs of the device are connected respectively with information and gate inputs of the first, second and third its input shift registers, the outputs of which through the corresponding buffer registers are connected to the corresponding inputs of the second major element whose outputs are information outputs of the device, strobe inputs of the first, second and third input shift registers are connected to the synchronous inputs of the first, second and third binary counters respectively whose reset inputs are connected to the gate inputs of the first, second and third buffer registers and the outputs of the first, second and third elements And, respectively, the first inputs of which are connected to the inverse outputs of the corresponding triggers of the first group, and the second inputs and information inputs of the first group triggers to the direct outputs of the corresponding triggers of the second group, respectively, the J-inputs of the corresponding triggers of the second group, respectively, are connected to the outputs of the first and second and the third decoder, the inputs of which are connected to the outputs of the first, second and third binary counters, respectively but, and the C-input triggers of the first and second groups and the synchronous input of the pulse distributor are connected to the output of the master oscillator, the reset inputs of the first and second groups of flip-flops are combined and connected to the output of the pulse distributor, which gates the output of the first element is connected to the information input of the pulse distributor. 2. The device according to claim.), Characterized in that the pulse distributor contains an element 541536 Both ipn and D-flip-flops are connected in series, the inputs of which are combined and connected to the forward output of the D-flip-flop of the higher order, whose information input is connected to the first input of the And distribution pulse element, and the inverse output to its second input, the synchronous inputs of the triggers The IQ is connected to the synchronous input of the distributor, and the information input of the low-order trigger is connected to the information input of the distributor, the output of which is the output of the element I. 1 FIG. g