SU1665526A1 - Digital data receiving device - Google Patents

Abstract

The invention relates to a technology for the transmission of discrete information and can be used in the organization of communication systems and computing systems with a common communication channel. The purpose of the invention is to increase the amount of received information. A device for receiving discrete information contains a master oscillator 7, a block 10 of decoders, a block 11 of elements And, receivers 12 discrete signals. The goal is achieved by introducing amplitude limiter 1, comparator 2, RS flip-flop 3, first, second AND 4, 6 elements, block 5 of shift registers, block 8 of counters, inverter 9. The device provides the ability to transfer information from N sources through one communication channel discrete signals. In addition, each device for receiving discrete signals will receive information that is intended only for it. 1 il.

Description

ABOUT

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The invention relates to a technology for the transmission of discrete information and can be used in the organization of communication systems and computing systems with a common communication channel.

The purpose of the invention is to increase the amount of received information.

The drawing shows a structural electrical circuit of the proposed device.

A device for receiving discrete information contains amplitude limiter 1, comparator 2, RS flip-flop 3, first element 4, block 5 shift registers, second element 6, master oscillator 7, block 8 counters, inverter 9, block 10 decoders, block 11 And elements, receivers 12 discrete signals.

The device works as follows.

A digital sequence arrives at the input of the device, to which the first bit is synchronizing and exceeds the logic level of the remaining 1 bits, which is caused by the need to ensure stable synchronization and high noise immunity. The sync pulse simultaneously arrives at the amplitude limiter 1, in which it is limited to the logical 1 other bits in order to distort the operation of the device elements, and at the second input of the comparator 2, where it is compared with the voltage Uon (the Don value is greater than level of logic 1, but less than the level of the sync pulse). As a result of this comparison, the output of the comparator 2 generates a signal of the logical 1, which is fed to the S input of the RS flip-flop 3, and translates it into one state, since the R input at this time has a logic O level.

With the occurrence of 1 at the first input of the first element I 4, a level-limited sync pulse and M marker pulses, through its second input, sequentially arrive at the information input of the shift register unit 5 and register by means of clock pulses fed to its clock input from the output of the master oscillator 7,

Thus, at the outputs of block 5 of shift registers, an (M – H) -discharge parallel code appears, and because the information on the channel number is carried only by M marker pulses, all of them arrive at the corresponding outputs of block 10 decoders, and the sync pulse from the (M + 1) -th output of the block 5 shift registers simultaneously goes to the control

the mode selection input of the 5 shift registers, providing a logic level 1 transfer it to the storage mode, to the reset input of the counter block 8, whose active level is the logic level O, thereby allowing the counting of clock pulses to its counting input from the master oscillator output 7, and finally, at the first input of the second element And 6,

0, as a result of which K information pulses pass through all the elements of the AND block 11 of the elements AND through the third input, since at this time there is also a logical 1 M code at its second input

5 marker pulses are decrypted by a block of 10 decoders, and out of all its N outputs, the active level appears on only one, namely, the one whose number is equal to the binary number applied to the input,

0 Then at the first input of the corresponding element AND block 11 elements AND there is a logical 1, thereby allowing the passage of information pulses through the second input to the input of the corresponding receiver 12 discrete signals. At this time, at the transfer output of the block of 8 counters, after the K-th clock pulse is counted, a single pulse is generated, which serves as a signal that all the K information pulses intended for the N-th receiver 12 discrete signals are received. By arriving at the R input of the RS flip-flop H, this pulse translates it into the zero state, corresponding to the expectation of arrival

5 new sync pulse, and invertor, were inverter 9, it is a logical level

Oh successively put all the exits

block 5 shift registers and through it (M + 1} th

parallel output - block 8 counters, and

0 also provides a zero level shift mode to the right of block 5 shift registers.

Claims (1)

Claims An apparatus for receiving discrete information, comprising a master oscillator, receivers of discrete signals and a block of decoders, the outputs of which are connected to the same inputs of an AND element block, in order to increase 0 volume of received information, two And elements are entered, a shift register register, an inverter, a block of counters, an amplitude limiter and a series-connected comparator and an RS flip-flop, an R-input and output of which are connected respectively to the output of a block of counters that are connected to the input of the inverter, and with the first input of the first element I, the second input and the output of which are connected respectively. with the output of the amplitude limiter whose input is connected to one input of the comparator, and with the information input of the shift register block, one outputs and the clock input of which are connected respectively to the inputs of the decoder block and to the output of the master oscillator, which is connected to the counting input of the counter block, the fault input of which is connected to the control input and another output of the block shift registers, which is connected to the first input of the second element And the second and third inputs and output 0 which are connected respectively to the output of the inverter, which is connected to the reset input of the shift register unit, to the output of the first And element and to other inputs of the And element block, whose outputs are connected to the inputs of the corresponding discrete signal receivers, while the other input of the comparator is the reference input of the device, whose information input is the amplitude limiter input.