SU1363209A1 - Priority device - Google Patents

Abstract

The invention relates to computing and may find application in systems using a variable service discipline. The purpose of the invention is to increase the speed of the device. A priority device differs from the well-known one in that it introduces analytic blocks for address codes according to the number of bits of the interrupt register and the synchronization block, with each of the analysis blocks being addressable. The codes contain a shift register, a counter, two triggers, a reference element and two elements I. In the device, the search time for queries with the highest priority is reduced. 2 Il. Ltd. OO to

Description

The invention relates to computing and can be used in systems using variable service discipline.

The purpose of the invention is to increase the speed of the device.

Fig, 1 shows a block diagram of the device; FIG. 2 is a block diagram of a synchronization unit.

The device contains address registers 1, blocks 2 elements AND, block 3 elements OR, element AND 4, groups of address inputs 5 of the device, block 6 synchronization, information inputs 7 of the device, installation input 8 of the device, register 9 interrupts containing triggers in each bit 10.11; the device also contains

units 12 analysis of address codes, each block 6 receives sync pulses.

one of which contains a shift register 13, a comparison element 14, a trigger 15, an AND 16 element, a counter 17, an AND 18 element, a trigger 19; The device contains information outputs 20 devices.

Block; synchronization (figure 2) contains the generator 21 pulses, the element And 22, the counter 23, the element And 24, the delay element 25, the element NOT 26, the elements And 27, 28, the element I1Sh 29.

The device works as follows.

Service requests from sources are recorded by register 9 on individual inputs 7 for each source. Registers store source addresses in the reverse order of their assigned priorities.

The search for applications with the highest priority is performed cyclically using blocks 12 clocked by the sync pulses of block 6. For this purpose, the address code of sources that recorded their requests for service in register 9 is compared, and the source with the smallest address code is preferred. The comparison of the address codes is carried out by converting the parallel address codes of the respective sources into a serial code with simultaneous comparison of the like bits of the specified codes.

As a result of comparing the address codes of the sources that recorded their requests in register 9, the source with the highest priority is determined, and at the output of the trigger 19 corresponding to | its block 12 a log is generated. 1, arriving at the corresponding block 2 and the reset input input of the corresponding register register 9. As a result, the address source through the blocks 2 and 3 is fed to the information outputs 20 of the device, and the register 9 register is zeroed. During

the next cycle of operation, determined by the sync-following pulse period, and when the output of block 6, the search for a higher priority application is combined in time with the output to

outputs 20 device source address.

Blocks 12 operate as follows.

To inputs a and b of block I2 from outputs

At output 6 of block 6, the number of impulses in one packet of the pulse sequence is equal to the number of bits needed to represent the largest address code in binary form. Preparation of block 12 for operation is carried out by a sync pulse (arriving at the input of block 12, which resets counter 17, sets

30. Trigger 24 is in the unit state and enters the address code of the source, coming from the outputs of the register 1, c. shift register 13. Shift register 13 is (p + 1) -digit,

35 whereby the address code is entered in bits 1, 2, -, p, and in (p + 1) - the size of the log is entered. VI, arriving at the output of the register, as which the unit output (p + 1) -th is taken

40 bit

Let the request pulses arrive at the inputs 7 of the device, transferring the corresponding triggers 10 to a single state. Sync pulse

45 of block 6, arriving at the synchronization input of interrupt register 9, flips the corresponding triggers 11 to the one state, the remaining triggers 11 are in the zero state.

50 Let the address codes of the sources with the numbers t, S and f in the binary representation have the values 1001, 1010 and 1101, while the priorities for servicing the sources are distributed in order of the opposite of the value of the address codes.

Comparison elements 14 generate pulses at the moments when the signals do not match at their inputs. After

entering the address codes of the respective sources into register bits 13 and the log. - in (p + 1) -th bit, at the outputs of all the shift registers 13. a log, 1, is set; Therefore, at the output of the element 4 there will be 1.

Thus, on both inputs i of all elements 14 a log is maintained. 1, and the triggers 15 remain in a single state.

In all blocks 12, except for those that correspond to incoming requests, elements 16 are locked by a log. Oh, coming from the outputs of the corresponding register bits 9. The sync pulses arriving at the inputs b of the blocks 12, to which the received requests correspond, pass through the elements to the shift inputs of the registers 13 and the counting inputs of the counters 17.

After entering the inputs of the shift registers 13 of the first pulse on

the outputs of the latter will appear logically in this cycle of operation of the device

signals that correspond to older sources of source address codes. For the example value under consideration

the highest bits of all codes are equal

I111t

i.

Thus, after a shift by one bit of codes, a log is sent to the inputs of the AND 4 element from the outputs of all the registers 13. 1. At the outputs of the comparison elements 13, a log is maintained. ABOUT.

The second clock pulse goes through the open elements 16 to the shift inputs of registers 13, as well as the counting inputs of counters 17, shifts the codes stored in registers 13 by one more bit. Logic outputs O and 1 are respectively set at the outputs of registers 13 element 4 is formed log. A. On both inputs of the two elements 14, the same logic signals are set (log. O); all other elements 14 fix a mismatch of signals at their inputs — a log appears at the outputs of the indicated comparison elements. 1, I throw non-corresponding triggers 15 to the zero state.

In block 12, the zero output signal of the trigger 15 locks the element 16, preventing further passage of clock pulses to the input of the shift of the register 13 and the input of the counter 17.

The third clock pulse of two blocks 12 passes through the open elements 16 to the inputs of the registers 13 and counters

 7At the output of the shift register 13

The first block 13 is a log; - O, and the output of the register 13 of the second block 12 is a log. I (these signals correspond to the values of the third bits of the codes).

The output signal of the element And 4 takes the value O. Consequently, the element 14 of the second block 12 captures the mismatch of the signals at its inputs and generates a log at the output. M, resetting the trigger 15 to O. Element 16 of this block is locked by the output signal of the trigger 15.

Thus, after the passage of the third pulse at the outputs of all the shift registers 13, except for one, the log is recorded. 1, with further shift codes in the specified registers

five

(3

will occur, since the corresponding elements 16, through which the shifting pulses pass, are locked.

The fourth pulse of the packet passes 0 through the element 16 to the inputs of the register 13 and the counter 17. At the output of the register

13 is set to log. 1 corresponding to the least significant bit of the code. The output signal of the element And 4 takes the value 1, and at the output of the element

14 is supported by the log. ABOUT.

In this example, only one counter 1 7 passed all impulses, h.a Eni to this counter. As a result, the output of the element And 18 appears log. 1. The impulse from the output of block 6 is fed to the D-trigger synchronous inputs 19 of all blocks 12, the corresponding trigger 19 is set to

5 single, and the rest -. to the zero state, the single output signal of the D-flip-flop 19 unlocks the corresponding block 2 and resets the corresponding triggers 10 and 11.

0 Address source code with the highest priority from the outputs of register 1 through the open unit 2 and unit 3 enters the information outputs 20 of the device and is maintained for

5 of the next cycle of the device.

At the outputs of register bits 9, corresponding to their unserved sources, the log is saved. 1. With the arrival of the sync pulse at the time of the log.

Claims (1)

1 also appears on those outputs of register 9, to the inputs of the triggers 10 of which from the inputs of the 7 device were received, the request pulses during the service of the previous requests. Then the next cycle of the device operation begins. Formula iso A priority device containing an interrupt register, a group of address registers, an OR block of elements, the element AND, a group of blocks of elements AND, the group of outputs of each register of the group address is connected to the group of inputs of the same name block of elements AND groups whose outputs are connected to the inputs of the block of elements OR, the group of outputs of which is a group of information outputs of the device connected to the corresponding groups of address inputs 20 ditch of the same name-bit register. interrupts, the single input of the first trigger of each bit of the interrupt register is connected to the corresponding information input of the register Device IDs, device information inputs are connected to a group of interrupt inputs 25, the output of the second trigger of the interrupt register, which distinguishes each bit of the interrupt register so that, in order to detect the corresponding output of the device’s speed, blocks of analysis of address codes by the number of bits of the interrupt register and a synchronization block, each of the blocks of analysis of address codes contains a shift register, a counter, two triggers, a comparison element, the first and second AND elements, and input shift register each address code analysis unit connected to the homonymous group register address outputs the interrupt register, the output of the second one, the trigger of each block of the analysis of the address codes is connected to the control input of the block of the same name of the elements of the group, the clock input of the second trigger of each bit of the interrupt register is connected to the second output of the block 2g sync. The third input of the first element AND each block of analysis of address codes is connected to the output of the first trigger of its block of analysis of address codes, the first input of the element groups, the first output of the synchronization block Q comparison of each ad- / analysis block connected to the input of the resolution of the recording of the shift register, to the reset input of the counter, to the single input of the liepBoro trigger and the synchronous input of the second trigger of each analysis block the 45th input of the comparison element of each codes, the second output of the synchronization block is connected to the first input of the first element AND of each block, and the address codes, the second input of which is connected to the output The address code analysis unit is connected to the output of the shift register of its analysis unit, the installation input of the synchronization unit is connected to the installation input of the device. of the same name bit of the interrupt register, the output of the first element I is connected to the shift input of the shift (- register and the counting input of the counter of its address code analysis block, the outputs of the counter are connected to the inputs of the second element I, the output of which is connected to the information 0 to the input of the second trigger, its address code analysis block, the interrupt register contains two triggers in each bit, with the output of the first trigger connected to the information input of the second trigger of its bit of the interrupt register, the output of the second trigger of each address code analysis block connected to the input . mi reset the first and second trigger of the same name-bit register register. interrupts, the single input of the first trigger of each bit of the interrupt register is connected to the corresponding information input of the register 5 interrupts, the output of the second trigger of each bit of the interrupt register is the corresponding output 25 interrupts, the output of the second trigger of each bit of the interrupt register is the corresponding output the interrupt register, the output of the second one, the trigger of each block of the analysis of the address codes is connected to the control input of the block of the same name of the elements of the group, the clock input of the second trigger of each bit of the interrupt register is connected to the second output of the block 2g sync. The third input of the first element AND each block of analysis of address codes is connected to the output of the first trigger of its block of analysis of address codes, the first input of the element Q Comparison of each unit of analysis ad- / The national codes are connected to the output of the element I, whose inputs are connected to the outputs of the shift registers, all blocks of analysis of address codes, the block of analysis of address codes is connected to the output of the shift register of its analysis block, the installation input of the synchronization block is connected to the installation input of the device.  2G - 22 5 synchronization block FIG. g