SU1663769A1 - Frequency-to-code converter - Google Patents

Abstract

The invention relates to automation and computing, in particular, to devices for processing signals from frequency sensors, and allows to simplify the practical implementation of the device by directly converting the frequency into a code. A converter comparing the codes and the fourth counter are entered into the converter containing three pulse counters, a trigger, two AND elements, an OR element, a frequency divider, an exemplary frequency generator. The input frequency signal is converted to a proportional code, which is fed to the outputs of the counter. 1 il.

Description

The invention relates to automation and computing, namely to devices for processing signals from frequency sensors.

The purpose of the invention is to simplify the practical implementation by reducing the technical means in the converter.

The drawing shows the functional diagram of the Converter.

The frequency converter in the code contains counters 1-4 pulses, block 5 comparison codes, trigger 6, elements AND 7, 8, element OR 9, frequency divider 10, reference frequency generator 11, input 12 and output 13 of the bus.

The Converter operates as follows.

Until the next pulse arrives at the input, trigger 6 is in the state when its direct output is 0. The outputs of elements 7, 8 are logical O, and the output of element 9 is 1. The counters 1, 3 are in the zero state , in the counter 2 - the number equal to the number of impulses of the generator 11, which came to the counter 2, the divider 10 from the moment of the arrival of the previous pulse on

input 12. At the output of counter 4, the code is directly proportional to the input frequency. When a regular pulse arrives at bus 12, a 1 is formed at the output of AND 7, which is fed to the output of the device synchronization and to the inputs of the installation in O counters 2, 3. The high potential at the output of the synchronization informs about the possibility of removing the input frequency code from the outputs of counter 4 . Counter 2 is zeroed in, counter 3 is confirmed by O.

After the end of the pulse on the input bus 12 at the output of the element And 7 O appears, prohibiting the removal of information from the output bus 13, the counters 2, 3 are ready to receive information. When pulse 10 appears at the output of divider 10, trigger 6 goes to state 1, and 1 is written to counter 2. At the output of OR 9, O appears, allowing information to be written to counter 1, and 1 , allowing the passage of pulses from the generator 11 to the inputs of counters T, 3. When writing one pulse to counter 1, the output of the comparison block 5 appears 1, which is recorded in

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Claims (1)

IT IS POSSIBLE SPIM, BCHDHOV 1 0 At a time from 1 kodog input frequency to signal 1 at the output Synchronization Formula of Invention The frequency converter in the code containing three pulse toigger pulse counters. the divisor is often and with the first input of the first element AND, the output of which is connected to the counting input of the PODEOIO mmpulse counter, the sieting input of the second pulse counter is combined with the input of a triter installation, characterized in that with a simplification circuit practical implementation, a paviemp code block and an impulse counter were introduced; the output of the overflow of which the connection — with the input of the second element | / L input — is set to the O flip-flop, by The PUSHRES of which are field are “city” for the input of the first element of the Peak to the input of the third pulse counter, and the inverse output is connected to the input of the OR element, whose output is connected to the input of the new pulse counter in O1, and the second input is combined with the third input the wnvnbcOB counter and is connected to the output of the comparison codes of the peov and vopo group codes the inputs of which are connected with the corresponding outputs of the first and second counters of the impulse, respectively, the output of the installation in O of the second and fourth counters of the pulses are combined, connected to The VUUYA of the second element And are the output bus of the Shinhoiiza1 and, the frequency separation of the gel is connected to the input of the 1 / gatero, the outputs of the third 81 ° pulse are the output output of the pert element of the fourth element pulse counter, the second input of the second element AND is the input bus