SU661748A1 - Intermediate storage of equalising type - Google Patents

Description

trigger, and the output of the clock generator is connected to the second input of the nth cell of the NAND, the output of which is the output of the device.

FIG. 1 is a schematic diagram of the device on the R-S type triggers, and the first r-k type; in fig. 2- time diagrams.

The device contains a cumulative register consisting of n synchronized triggers I-4, with trigger 1 having an additional asynchronous input g, AND-NE 5-8 cells, and a generator of 9 sync pulses. The timing diagrams shown in FIG. 2 correspond to the following points of the device. 10 - at the device input, 11, 13, 15, 17 - at the direct outputs of the flip-flops 1-4, respectively, 12, 14, 16 - at the outputs of the AND-NE cells 5 -7, respectively, 18 - at the output of the clock generator 9 and 19 - at the output of the device.

The device works as follows.

Let at the initial moment the trigger 1-4 of the register be in the state O, i.e., logical O is set at their forward outputs, and logical 1 is set at the inverse outputs.

At the indicated state of the flip-flops, the outputs of the cells 5-8 are set to logical 1. The presence of a logical O at the direct output of the flip-flop 4 is a prohibition for the output of the IS-NE 8 cell, which is the output of the device, and the generator 9 pulses.

When the first pulse arrives from the stream randomly distributed to the counting input of trigger 1, the latter through time tz, equal to the transition time of trigger 1 from one stable state to the second, will transition to state 1, as a result of which the output of the AND-HE cell 5 through time TI equal to the propagation time of the signal in the cell IS-HE 5, the logical value is 0. This in turn causes the time tz. reset trigger 1 to its original state. Upon returning to the initial state, trigger 1 will be set to state 1, trigger 2, so that at the output of the cell IS-NE 6 a logical O appears in time t, and this in turn, similarly to the first, causes the initial state to return to ti the At the same time, the next trigger 3 will go to state 1, etc., all subsequent ones. The process continues until it goes into state 1 n-th trigger 4. The presence of a logical O at generator output 9 in the intervals between two output pulses of the generator is a prohibition to return the n-th trigger 4 to its initial state.

If a second impulse arrives at the device input, then this impulse, changing the state of the triggers from 1 to n-2-nd twice (not shown in Fig. 1), will result in state 1-1-th trigger 3. Presence logical

At the inverse of the output of the nth trigger 4, it is forbidden to return the trigger 3 to the initial state. Thus, each of the subsequent pulses arriving at the input of the device will alternately transfer to state 1 the triggers from the nd-2nd to the 1st, registering π-pulses.

The arrival of the n-f of the 1st pulse does not change the state of the 1st and subsequent triggers, since the presence of a logical O at the asynchronous trigger input is a sufficient condition for its presence in state 1.

With the arrival of a pulse from the output of the generator 9 to the output of the nth cell of the AND-NE 8 in time ti is logical O, which causes the time that the n-th trigger 4 returns to its original state, and this in turn again terminates the logical O at the output of the IS-NE cell 8. At the output of the IS-HE cell 8, a negative pulse with a duration of t pg (+ tg, coinciding in time with the output pulse of generator 9 and being the output pulse of the device) will obviously be received.

The occurrence of a logical 1 on the inverse output of the nth trigger 4 (when it returns to the initial state) causes the occurrence through the time ti of logical O at the output of the n-1st cell IS – NE 7 and the return through time Ta to the initial state n-1st trigger 3. This again sets state I to nth trigger 4, and logical 1 at the inverse output of trigger 3 causes a return through time t fi + g, to the initial state of p-2 trigger.

At the same time, it will again return to the state of 1 n-1st trigger 3. Then it will transition to the initial 5 state and back to the state of 1 n-2 trigger, etc.

The pulse 9 triggered by the impulse generator 9, which is triggered to its initial state, will then continue until the first triggers from the second to the fifth state are established and the initial state of the trigger is 1, t. e. with the arrival of the first impulse of the generator 9, after the completion of the transient processes, the first trigger 1 returns to its initial state.

With the arrival of the next pulse from the output of the generator 9, the second pulse will pass to the output of the device, and the 2nd trigger 2 will return to the initial state until the moment all n triggers return to the initial state and the number of pulses at the output of the device becomes the number of pulses entering the input.

A feature of the proposed device 5 is the need to satisfy the conditions gE 2 (t (+ tz) and TI Gg, where m3 is the pulse duration of the generator 9.

The second condition is fulfilled by using AND-HES cells with a signal propagation time ti in them longer than the transition time gy from three stable states to another.

If this condition is not observed, the output of the device of an unbounded pulse is possible if state 1 contains at least the last two triggers 3 and 4.

The assumption of a certain initial state of the register triggers is not a necessary condition for the normal functioning of the device, since in the absence of signals at the device input, all the triggers through time, where is the period of the generator 9 pulses, will be in the initial state.

Unlike the device described in 3, in which cumulative registers with e 1 memory n-1 are used, where with the arrival of the n-th input pulse in the interval between two pulses of the clock generator, n-1 pulses may not be registered immediately, Only n + 1 and subsequent pulses will not be registered with the proposed device.

The number of triggers in the proposed device is selected based on the permissible error of the device, the maximum average frequency of the statically distributed pulses, and the averaging time t.

When testing the device, the following results are obtained. The error of the device with an average frequency of statistically distributed pulses of 1500 Hz, the pulse period from the output of the sync pulse generator 200 µsec and the duration of these pulses 0.12 µsec was 0.72% when 3 triggers were used in the device and 0 when 4 triggers were used.

The device is quite simple, does not require special configuration.

and is easily implemented on commercially available industrial microcircuits, for example, the 133, 134, 155 series, which allows to realize a reliable small-sized device operating in the range of ambient temperatures from minus 60 to plus 125 ° C.

Claims (3)

1. US patent number 3745.346, cl. 250-83.3R, 1973. 2. US patent number 3.752.988, cl. 250-270,1973. 3. US patent number 3.720.910, cl. 340-18R, 1973.