SU375797A1 - MULTI INPUT COUNTER OF PULSES - Google Patents

Description

one

The invention relates to a pulse technique and can be used when calculating the total number of pulses of several pulse streams.

Multi-input counters are known that calculate the total number of pulses arriving at several inputs. These counters contain a counting register, memory cells, pa, triggers, and a polling circuit. The survey design is a chain of "I. The second input of each element "And is associated with the zero output of the memory trigger corresponding to it, and the output of this element" And, moreover, is connected with the bullet input of the next trigger.

The known device is intended to operate under conditions B when the pulse arrival period PA each of the inputs ne exceeds the resolution of the counting register divided by the number of inputs

t

T P12, i.e., pulse arrival frequency

The switches are quite small, or when the frequency of arrival at one of the inputs exceeds the specified limit, provided that at some other input the frequency decreases accordingly. If, on the other hand, the arrival frequency of the pulses exceeds the limit on several inputs without a corresponding decrease in other inputs, then the use of this device results in a loss of input pulses. The aim of the invention is to increase

speed counter operation. The goal is achieved by connecting one “And” element and interrogation circuit with each previous pair of memory triggers, connecting the outputs of this pair of triggers with inputs of half-summators, which through the elements “OR are connected with a counting register.

The drawing shows the proposed counter. It contains memory triggers / - 5, polling circuit 6, formed by series-connected elements “And 7 and 8, half-combiners 9 and 10, elements“ OR 11.12 and counting register 13, formed by the serial connection of triggers 14, 15 and 16. Unit halves triggers are labeled

hatching. To the inputs of the element OR 11, the direct outputs of the half adders 9 and 10, and to the element OR 12 there are transfer outputs of these half adders. In the initial state, the triggers 1-5 are in the zero state, so that at the zero outputs there are high potentials. When a counting pulse arrives at any input of the device corresponding to this input, the trigger goes into a single

condition, and high potential moves

from zero to single output of this trigger.

The input of the polling circuit 6 is supplied with interrogating pulses with a frequency close to the resolution of the counting register 13. Suppose that the input of the polling circuit 6 receives the next interrogating pulse, which falls on the zero inputs of the trigger 1 and 2 to the input of the element "And 7. Suppose also that by the considered time the triggers 1 and 2 (one or both) are in a single state. Therefore, there is no potential at the zero output of the K1 extreme measure of one of these triggers and, therefore, the polling pulse will not be able to pass through the element AND 7. The same impulse falling on the zero inputs of the triggers / and 2 transfers them to the zero state. If in the single state there was only one of these triggers, then this trigger goes to the zero state, and the state of the other trigger is only confirmed. Due to the fact that the triggering of the trigger is somewhat delayed relative to the time of arrival of the throwing pulse, the signal from the input element "And 7 does not have time to go to its output (if this delay is not enough, corrective delays can be used).

When a trigger transitions from a single to a zero state, a voltage front appears at its zero output, exciting the corresponding input of the half adder 9. If there are both 1 R 2 triggers in the unit state, then both inputs of the half adder are excited at the moment of appearance of a polling pulse in a single state, there is only one of the triggers / or 2, the signal appears at the output of the half adder 9 and through the element OR // enters the input of the first trigger 14 of the register 13. Thus, to the number written in this register e is added unit. If, on the other hand, there are both triggers / and 2, the signal from the transfer output of the half adder 9

enters the counting input of the trigger 15, which is the second trigger of the register 13. This means that a number two is added to the number written in the register 13. Since both 1 to 2 flip-flops are now set to the zero state, the next polling pulse freely passes through the element 9 and enters the next AND 10 element and the zero inputs of the triggers 3 and 4.

If the state in the unit is one of these triggers, the signal goes to trigger 14, and if both triggers in the unit, then trigger 15. In the first case, one is added to the number written in register 13, - number two.

Consequently, each polling pulse, which is input to the polling circuit input, polls two triggers at once, i.e. the number of inputs to the circuit can be doubled, or

the same number of inputs, the sampling time can be reduced, which allows to increase the frequency of the input pulses compared to the corresponding value of the input frequency of the prototype.

Subject invention

A multi-input pulse counter containing counting triggers, storing triggers and elements AND, connected in series, characterized in that, in order to improve the speed of the device, it contains half-summators and elements OR, and zero outputs of each pair of memory triggers are connected to the inputs of the corresponding them "And, the output of which is associated with the zero inputs of the next pair of mating triggers, the zero outputs of each pair of flip-flops are connected to the inputs of the half summators, the direct outputs are half summator They are connected to the inputs of the first OR element, the transfer outputs to the inputs of the second OR element, and the outputs of these elements are connected to the counting inputs of the first and second counting triggers, respectively.

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