SU372667A1 - DEVICE FOR CHANGING THE PERIODS OF THE FOLLOWING - Google Patents

Description

one

The invention relates to the field of radio engineering, in particular to a pulse technique.

Devices are known for changing pulse pulse periods, which contain a divider of the secondary frequency, a matching circuit, and a memory counter-register, which allow receiving a signal ic by a pulse-following period, which varies in a stepwise sawtooth manner. The signal at the output of such devices is a sequence of pulses, each after the subsequent period of which differs from the previous one, and the time period of the sitnal entering the input of the device. The pulse periods at the output of known devices vary from a value equal to the period of the input pulses to a value equal to the product of the period of the input pulses and the capacitance of the reference frequency divider.

A disadvantage of the known devices is that they form a signal with the asymmetrical law of variation of the output pulse periods.

The purpose of the invention is to create a device that allows the change of periods of the investigation of impulses according to a symmetrical law.

The proposed device additionally introduces the schemes “AND,“ OR, and a sign path, the input of which is connected to the output of the counter

memory register, and the output of each pz of the trigger of the memory counter-register is connected to the first input of the corresponding AND circuit, the second inputs of the AND circuit are connected to the outputs of the sign trigger, and the AND circuit connected to the outputs of the same / th trigger of the memory register-register are connected to the different outputs of the sign trigger, and the outputs of these circuits | "AND through the scheme" OR connected to the installation output of the / th three registers of the reference frequency, where / 1, 2. 3 ,. . ., P.

FIG. 1 shows a diagram of the described device; in fig. 2 - the same, with n 2.

Divider / reference frequency contains sequentially enabled triggers 2i, 2,. . ., 2-n with counting inputs, and counter-register 3 of memory consists of i-s (sequentially connected flip-flops 4i, 4, ..., 4n with counting inputs. The output of count-register of memory is connected to the counting input of trigger 5 .

Each output of each trigger of the memory register counter is connected to the input of its own “I.

Left exits triggers 4, 4,. . ., 4n are connected. With the inputs of even circuits "And (6, b, ..., 6"), the right outputs are three pgres 4i, 4 ,. . ., 4p are connected to the outputs of the odd “AND

(6,, 6 ,, ..., 6g,).

The left trigger output 5 characters - connected with the second inputs of even circuits "And (62, 6, ..., 6p), and the right - with the second inputs of odd circuits" And (5i, 63, ..., 6p).

The output of the reference frequency divider is connected; with the input of the counter-registr. ra 3 -pam tee and with the third inputs of all circuits "And (6-2, 6i, 6ts, bz, ..., -bp). The output of the circuits “AND (i and bg), whose inputs are connected to the trigger 4 of the memory counter-register, through the circuit“ OR 7 is connected to the installation input of the trigger 2 of the divider of the reference frequency; the outputs of the circuits “And (bz and 4), whose inputs are connected to the trigger 4z of the counter-register. Tam, through the circuit“ OR 72 are connected to the installation input of the trigger 2 divider of the reference frequency, and so on. In the General case, the outputs of the circuits “And The inputs of which are connected to the outputs of the i-th trigger of the register-memory counter, through the "OR connected" to the setup input of the r-divider of the reference frequency divider.

The device works as follows. For simplicity, suppose that "2, and generally n can be any integer positive NUM.M.

Let the triggers 2i, 2, 4-i, 2 and 5 be in zero states at the initial moment. The input signal of the reference frequency with a period T of the pulse following arrives at the input of the reference frequency divider. The even And schemes (6 and 64) are prepared by a 5-digit trigger for passing the signal, and the odd And schemes (5i and 5h) are not prepared for passing the signal.

| At the output of the reference frequency divider at the moment of its overflow, a pulse appears, i.e., after 2 periods of the input signal. The first period of the output signal is 22-7 47. The impulse from the output of the reference frequency divider, which originated through the aperture 4G, is fed to the input of the memory counter-register and to the inputs of the And () circuits.

The counter-register memory will change its state to one. If previously the state of the counter — the memory register on the left-hand collectors was (00), now it is 10. As a result, only the output of one AND 62 circuit shows a signal that through the OR 7i circuit goes to the setup input Tgrigger 2 and thus change the state of the divider of the reference frequency by one, i.e., until the next pulse arrives at the device input, divider 1 will register the status of “one (10)”, and therefore the overflow pulse of the divider / at its output through the period () -T ZG. This impulse is again fed to the input of the memory counter-register and to the “AND (6i-64)” inputs.

Thereafter, the state of the memory counter register will again change to one. It will now have a two-by-two (01) saface number. The impulse from the output of the divider 1 hr-scheme “AND 64, the scheme“ OR / 2 will write “units to the trigger 22, i.e. before the arrival of the next

the impulse to the device input in the divider / will be recorded the number "two (01), and, consequently, the impulse overflow pulse is recorded at its output through the period () -T 27. As a result of the next operation cycle by the time of the next impulse input to the divider input it will record the number “three (11), and the pulse at the output of the device according to a period,. equal () -1 1.

By this time, the number of pulses equal to its capacitance (four pulses) will arrive at the input of the memory register counter, and the memory overflow signal at the output of the memory register register, which, arriving at the counting

the trigger input 5 characters, changes its state to the opposite. After the flip-flop of the 5-digit sign, the odd And schemes (5i and bz) are prepared to pass signals, and the even And schemes (62 and 64), which were previously prepared to pass signals, will not be able to pass them. By the same time, i.e., after the formation of the period between the output pulses, -equal T, the counter-memory register will be fixed, but the number (00) on the left trigger outputs, however, the left trigger outputs no longer participate in the work, since the AND schemes (6h and 6) are not prepared to pass the signals.

On the 1 right outputs of the triggers 4 and 4, respectively, the number “three (1, 1) will be fixed, i.e., until the next pulse arrives at the device input through the schemes“ AND (6 and 3), the schemes “OR (7i and / 2 ) in the divider / will be

the number "three (11) is recorded, i.e., the pulse of the overflow of the divider is over a period of (2" -3) -T.

The impulse from the output of the divider / will go to the input of the counter - memory register and to the input

schemes “And (). After that, the state of the memory counter register will again change to unity. On the right outputs of triggers 4 and 2, the number “two (01) will be registered for | this number“ two through the scheme “I bz, the scheme“ OR

/ 2 will be transferred to the divider L Pulse at the output of the device according to a period of () .7 2Г, and so on. d.

Thus, the symmetric law of variation of the periods of the output pulses is obtained.

Subject invention

A device for changing pulse periods, containing a reference frequency divider, consisting of triggers, a memory counter-register, and schemes, characterized in that, in order to obtain a symmetrical law of variation of pulse periods, the device becomes additional The “AND,” OR and a character trigger are introduced, the input of which is connected to the output of the memory counter register, and the output of each of the memory counter-register triggers is connected to the first input of the corresponding AND circuit

the second inputs of the circuits "And connected to the outputs of the trigger of the sign, -irncham schemes" And connected to the outputs of the same Mr. the trigger of the counter-register and they are connected to

different outputs trigger.ra sign | Ka, and the outputs of these circuits "And through the circuit" OR connected to the installation input of the n-th trigger of the divider of the reference frequency, where i I, 2, 3,. . ., P.