SU883910A1 - Parallel code parity checking device - Google Patents

Description

A disadvantage of the known devices is their complexity. It is also known a device for controlling a parallel binary parity code containing two AND elements, shift registers, the information inputs of the device: the parallel inputs of the shift register, the zero bit outputs of which are connected to the inputs of the first element AND, the output of which is connected to the first the input of the second element is And, the second input of the second element is AND is connected to the clock frequency bus, and its output is connected to the shift register shift input, the output of KOTQporo is connected to the counting trigger input, the output of the trigger is output y troystva 3. The disadvantage of this device is a low speed, taking into account the position of the unit due to significant bit code. The closest in technical essence and achievable positive effect to the proposed invention is a device for controlling a binary parity code containing an AND element, the first inputs of which are connected to the outputs of the corresponding controlled bits, an OR element whose inputs are connected to the outputs of the AND elements , pulse distributor and fixing trigger, the counting input of which is connected to the output of the OR element, and its zero input is connected to the first output of the pulse distributor, the other outputs of which are connected And the disadvantages of the known devices is its complexity and low speed of operation, due to the need to interrogate all bits, including those in the zero state, as well as the need special zeroing of the corresponding bits after completion of the parity code i process, as a result of which the readiness to control the next code pattern is slowed down. The purpose of the invention is to increase the speed of a device for controlling a parallel parity code. The goal is achieved by the fact that a device containing a register, a group of AND elements, an OR element, a trigger, and the information outputs of the device are connected to the single inputs of the register connected to the first input of the corresponding AND element of the group, the output of each AND element of the group is connected to the zero input of the corresponding register bit and the corresponding input of the OR element, the output to is connected with the counting input of the trigger, whose outputs are the outputs of the device, the AND element and the NAND element are entered into it, the clock input of the device is connected to the first input of the AND element, the output of which is connected to the second input of the AND elements th bit of the register is connected to the corresponding input of the NAND element and to the (K + 2) -th inputs of the AND elements of the group from (K + 1) year of the n-th, the output of the AND-NE element is connected to the second input of the AND element The essence of the invention is to simplify the device, which is achieved exclusion m distributor pulses removal information is performed in the arrival time clock pulses at a first input member I. In addition, the performance of the device is increased due to the removal count and status information bits of the registers which have a one value. Elements And the corresponding register bits are designed to retrieve information from those register bits that have unit values for the arrival of clock pulses from the output of the newly entered AND element, while connecting the zero outputs of the triggers of each previous register bit with the inputs of the AND elements of the group Subsequent discharge of information is produced in order of increasing register bits, starting with the youngest. After the information is removed, the corresponding bit is registered and the next element AND group is prepared for the information from the next higher register bit. The NAND element is intended to form a permitting signal at the input of the AND element, which ensures the passage of clock pulses to the inputs of all AND elements of the group. When the register is reset, a signal is issued to prohibit the passage of pulses of the clock frequency and readiness of the register for reception to control the next code. The OR element is designed to receive information about the unit values of bits and count them on a trigger with a counting input. The drawing shows a functional diagram of the proposed control device. The device contains inputs 1 code, register 2, the element FROM, the clock input 4, the element AND-NOT 5, the group of elements AND 6-9, the element OR 10 and the trigger 11 with the counting input. Register 2 is designed to store a monitored code entering inputs 1. Unit outputs (ka) are connected to the first bit of register 2, with the first inputs corresponding

elements AND 6–9 groups of elements AND subsequent bits of register 2. Zero output of the first bit of register 2 is connected to the input of the element. AND 7 of the second bit, element AND 8 of the third bit and so on, including element And 9 of the last bit code and element I-NB 5, the zero output of the second bit of register 2 is connected to the input of the element And 8 of the third bit, the element And 9 of the last bit of the code and the element i-NOT 5 and that further. The zero output of the last bit of register 2 is connected only to the input of the element AND-NOT 5. The output of the element AND-NOT 5 is connected to the second input of the IZ element, the first input of which is the input of the clock frequency 4, the output of the And 3 element is connected to the inputs of the And 6 elements - 9 groups of elements AND the corresponding bits of the register 2. The outputs of the elements AND 6–9 of the group of elements AND are connected to the inputs of OR 10 and the zero inputs of the flip-flops of the register 2 of the corresponding bits. The output of the element OR 10 is connected to the counting input of the trigger 11 whose outputs are the outputs of the device.

The device works as follows.

In the initial position, the register 2 is in the zero state and at the output of the element AND-NE 5 there is a potential prohibiting the passage of the clock pulses from the input 4 through the element 3 to the elements 6-9. The trigger with counting input 11 is also set to zero.

The monitored input in parallel form is fed to the informative inputs of register 2 and recorded in it, while the state of register 2 changes relative to the initial zero state and at the output of the AND-NE element 5 there appears the potential to allow the passage of clock pulses the first input 4 elements And 3, on elements And 6-9 groups of elements And for retrieving information about the unit value of certain bits of the register 2.

If code 0101 is recorded in the register, the signal arrives at the output of the NAND 5 element, arriving at the second input of the element 3 and allowing the clock frequency to pass through the first input 4 of the element 3. And enters the input elements And 6-9. However, the collection of information about the unit value of the bits of the register 2 is performed only from the first bit due to the inhibit signal fed to the elements AND 7-9 from the zero output of the first bit of the register 2.

The first clock pulse performs the retrieval of information about the unit value of the first register bit 2, enters through the element OR 10 at the counting input of the trigger 11, transferring it to the unit value. Simultaneously, the signal from the output of the element And 6 enters the zero input of the trigger of the first bit of register 2, sets it to the zero state and thus prepares the elements And 7-9

0 to retrieve information from a sequence of bits. The second clock pulse carries out the retrieval of information about the single value of the trigger of the third bit of register 2, since the element

5 and 7 is closed due to the low potential coming from the single output of the second bit of the register.

Thus, information is retrieved from the third bit of the register. The signal from the output of the element AND 8 enters through the element OR 10 to the counting input of the trigger 11 and switches it, simultaneously setting the trigger of the third bit of register 2 to the zero state. Register 2 is reset, at zero outputs of which high potentials occur, acting on an IS-NE 5 element, a signal from the output of which prevents the passage of pulses.

0 elements FROM.

After the arrival of the clock pulses, the state of the trigger 11 indicates how many pulses (even or odd has passed to its input, i.e., the evenness or oddness of the code being monitored can be determined from the state of the trigger. Frequency, how many bits of the code have a single value.

The speed of the proposed device depends on the number of units in the code, while in the code known for the control it is necessary to submit

5 (n- + 1) clock pulses, where n is the code width, which indicates a higher speed of the proposed device, and exclusion from the pulse distributor circuit allows

0 to simplify the design of the device.

Claims (1)

Invention Formula 55 A device for controlling a parallel parity code, containing a register, a group of AND elements, an OR element and a trigger, with the information inputs of the device connected to the single inputs of the register, a single the output of each register bit is connected to the first input of the corresponding AND group element, the output of each AND group element is connected to zero 65 of the cooTBeTCTsyjomero input of the register register and with the corresponding input of the OR element, the output of which is connected. The trigger, the output of which is the output of the device, is so that, in order to improve performance, the DEVICE contains an element AND vcTnor Р clock input “By the primary input of the element and whose output is connected to the second inputs of elements AND groups, the zero output of the k-th register bit is connected to the corresponding input of the AND-NAND element and to (to + 2) -th inputs of 10 elements AND group from (K + 1) -th to the n-th, the output element AND-NOT connected to the second input the house of element I. Sources of information taken into account in the examination of U USSR certificate 382090, cl. G About F 11/10. 1972. m certificate of the USSR 552609, cl. G 06 F 11/08, 1977. I t; o; -, USSR certificate No. 530332, cl. G 06 F 11/10, 1977 certificate of the USSR No. 42.8385, cl. On F 11/10, 1975 (prototype). S Yu