SU1156251A1 - Multistage counter with check - Google Patents

Abstract

1. A MULTIPLE COUNTER WITH A CONTROL, each cascade of which contains the first element SH1I-NOT and a counting unit, the clock input of which is connected to the output of the first element SH1I-NOT, the first input of which in all stages except the first one is connected to the transfer output of the counting unit of the previous stage , the first and second inputs of the first element OR — NOT the first. cascade are connected respectively to the input bus and to the output of the AND element, the first and second inputs of which are connected respectively to the output of the second OR-NOT element and to the output of the imp generator pulses, characterized in that, in order to increase the control accuracy, a control unit is inserted into each cascade, and an AND element and a second OR-NOT element are entered into the cascades, the output of which is connected to the first input of the AND element, the second the input and output of which is connected respectively to the output of the pulse generator and to the second input of the first element NLI-NOT; each section, the information outputs of the counting unit are connected to the inputs of the control unit, the outputs of which are connected to the inputs of the second element OR NOT. 2. Counter POP.1, characterized in that each control unit contains a decoder having N) outputs, N elements NOT ,. M-1 of the elements OR, N-1 of the first elements 8 (L I and N-1 of the second elements AND, each i-th output (, 2, ..., N) of the decoder is connected to the input of the i-ro element NO, the output of which , besides the last, is connected to the first input of the corresponding i-ro of the second element AND, the second input of which is connected to the output of the corresponding {th element OR and to the first input of the corresponding i-ro first element AND,; the second input and output of which are connected respectively to the output (i + 1) -ro of the element NOT and the first input of the i-ro element OR, the second input of which is connected to the iM output of the decoder The inputs of which are connected to the inputs of the control unit, the corresponding outputs of which are connected to the outputs of the second And elements and to the last output of the decoder.

Description

The invention relates to automation and computing and can be used to monitor the performance of the meters. A device for testing a multi-stage counter is known, each stage of which contains an HJIH-HE element and a counting unit, the clock input of which is connected to the output of the OR-NOT element, the first input of which is connected to the transfer output of the counting unit of the previous stage, the second inputs of III-NOT elements are connected to output element H, the inputs of which are connected to the output of the pulse generator and the output of the multi-input element OR NOT, the inputs of which are connected to the output of the counting unit of all channels}. A disadvantage of this device is low control accuracy. Closest to the proposed is a multi-stage counter with control, each stage of which contains the first element OR NOT and a counting unit, the clock input of which is connected to the output of the first element OR NOT, the first input of which in all stages except the first is connected to the output transfer the counting unit of the previous cascade, the first and second inputs of the first element JIP-NOT of the first cascade are connected respectively to the input bus and to the output of the element I, the first and second inputs of which are connected respectively to the output of the second element nta OR OR NOT and with the output of the pulse generator, the output of the element I is connected to the second inputs of the first elements of the STI-NOT of the other stages, in each cascade the output of the counting unit is connected to the input of the display unit and the corresponding input of the second element OR NOT the first stage t2l . A disadvantage of the known device is the relatively low control accuracy. This is due to the fact that it is not possible to determine at which tact the counting block of one of the channels failed. The purpose of the invention is to improve the accuracy of the control. The goal is achieved by the fact that in a multi-stage counter with control, each stage of the kotoro Contains the first element of the IPI-NOT if the counting unit, the clock input of which is connected to the output of the first element OR-NOT, the first input of which in all stages except the first connected to the transfer output of the counting unit of the previous stage, the first and second inputs of the first element OR NOT the first stage are connected respectively to the input bus and to the output of the element And, the first and second inputs of which are connected respectively to the output of the second el of the OR-NOT unit and with the output of the pulse generator, the control unit is inserted into each cascade, and the AND element and the second OR-NOT element, the output of which is connected to the first input of the AND element, the second input and output are connected, are entered into the cascades. in accordance with the output of the pulse generator and with the second input of the first element OR NONE, in each section the information outputs of the counting unit are connected to the inputs of the control unit, the outputs of which are connected to the inputs of the second element OR NONE. In addition, in a multi-stage counter with control, each control unit contains a decoder having N outputs, N NOT elements, N -1 OR elements, N-1 first AND elements and N-1 second AND elements, each 1st output (i 1 , 2, ..., Yu of the decoder is connected to the input of the i-th element NOT, the output of which, except the last one, is connected to the first input of the corresponding 1st second element AND the second input of which is connected to the output of the corresponding i-ro element OR and to the first the input of the corresponding 4th first element And the second input and output of which are connected respectively at the output (i + 1) -ro of the element NOT and the first input of the ith element OR, the second input of which is connected to the th output of the decoder, the inputs of which are connected to the inputs of the control unit, the corresponding outputs of which are connected to the outputs of the second elements And the last output of the decoder .. The drawing shows a diagram of a multi-stage counter with control. The drawing shows: 1 pulse generator, three-stage counter 2, counting blocks 3 1 - 3 "3, first elements - 4" 3 IPI-IE; blocks 5: control, the second elements - SH-YE, elements. In the drawing, the clock inputs of the counting units - 3 3 are connected respectively with the outputs of the first elements 4. ILIH-HE, the first inputs of which are connected respectively to the input bus and to the transfer outputs of the counting blocks, the information outputs of the counting blocks are connected respectively to the inputs of the blocks - the branch outputs of which are connected respectively to the inputs of the second elements - OR-NOT, the outputs of which are connected respectively with the first inputs of the elements are AND, the second inputs of which are connected to the output of the pulse generator 1, the outputs of the elements AND are connected respectively to the second inputs of the first elements OR OR NOT. Each Of the blocks - control contains a decoder 8, having, for example, four outputs j elements - NOT; the first elements And; elements - OR and the second elements - I. In addition, the counter has an input bus 13 In each of the blocks, control first, second, third and fourth outputs of the decoder 8 are connected respectively to the inputs of the elements - NOT; the outputs of the elements are NOT connected respectively to the first inputs of the second elements - AND, the second inputs of which are connected respectively to the outputs of the elements - OR and connected respectively to the first inputs of the first elements - AND, the second inputs of which are connected respectively to the outputs of the elements - NOT, the outputs of the first elements - AND respectively, they are connected to the first inputs of the elements 11 1 - ШШ, the second inputs of which are connected respectively to the first, second and third outputs of the decoder B, whose inputs are connected to the inputs of each block s - control, the outputs of each of which are connected to the outputs of the second elements And and the fourth output of the decoder 8. In each of the blocks - 5 3 pairs of elements,,,, and, 11 "3 are installation triggers, and the trigger is set to a single state by a positive impulse that arrives at one of the inputs of the corresponding (their elements are < 1 > and is set to the zero state by negative impulses, arriving at one of the inputs of the corresponding elements —I. The device operates as follows. In the initial state, all the blocks of counter 2 are zeroed, at the outputs of the blocks of control there are also zero signals, and the elements AND are open for passing counting pulses to the counting blocks of. The control of all blocks is carried out in the same way. . Work is considered on the example of one counting block. In the initial state, the content of the counting block is zero and on the first output of the decoder 8, a single signal that writes a trigger on the AND, OR one and simultaneously inverting the element NOT, the second element I locks. Upon the arrival of the first counting pulse, the block becomes equal to 1, and a single signal now appears at the second output of the decoder 8; having inverted the corresponding NOT element, it sets the trigger on the AND, OR elements to the zero state and closes the corresponding second element I. At the same time, the unit is written to the trigger formed by the OR element and the first element I. When two pulses pass, the control unit appears to be zero signals. The next third sets the block content to three. At the fourth output of the decoder 8, a single signal appears, which is fed to the input of the OR-NOT element, and the counting stops. At the same time, this signal, which is inverted by the corresponding element NOT, erases the unit in the trigger. Thus, in the case of correct operation in the block, the content is equal to three and only at the last output of the control unit — a single signal that indicates the correct operation of the counting unit 3 1. In the event of a failure, the sequence of occurrence of pulses at the outputs of the decoder 8 is violated, then that the corresponding trigger is not reset to zero, the output of the corresponding

I 1

an element — a single potential appears, and an entry. the pulse counter from generator 1 to the counting unit is terminated. At a single potential at the corresponding output of the block, you can determine the number of the clock pulse at which the failure occurred.

In the case of correct operation of the counting units - after blocking the elements - AND the corresponding signals from the outputs of the elements - OR NOT possible to check

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the chain of transfers of blocks, codes, one impulse across bus 13, the counting 1e blocking must go to the initial state, the blocking signals from the outputs of the elements OR OR NOT disappear and the monitoring cycle repeats.

Thus, the introduction of new design features improves the accuracy of control of meter bits, which favorably distinguishes the proposed device from the prototype device.

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Claims (2)

1. MULTI-Cascade COUNTER WITH CONTROL, each stage of which contains the first OR-NOT element and a counting unit, whose clock input is connected to the output of the first OR-NOT element, whose first input in all stages except the first is connected to the transfer output of the counting block of the previous stage , the first and second inputs of the first OR-element of the first stage are connected respectively to the input bus and the output of the And element, the first and second inputs of which are connected respectively to the output of the second OR-NOT element and to the output of the pulse generator characterized in that, in order to increase the accuracy of control, a control block is introduced into each cascade, and in cascades, starting from the second, an AND element and a second OR-NOT element are introduced, the output of which is connected to the first input of the And element, the second input and output which is connected respectively to the output of the pulse generator and to the second input of the first OR-NOT element, in each category the information outputs of the counting unit are connected to the inputs of the control unit, the outputs of which are connected to the inputs of the second OR-NOT element. 2. Counter pop. 1, characterized in that each control unit contains a decoder having N outputs, N elements NOT. N-1 elements OR, M-1 first elements And N-1 second elements AND, each i-th output (1 = 1,2, ..., N) of the decoder is connected to the input of the ί-th element NOT, the output of which, except the last one, it is connected to the first input of the corresponding ΐ -th second AND element, the second input of which is connected to the output of the corresponding ΐ -th OR element and to the first input of the corresponding ί -th first AND element,; the second input and output of which are connected respectively to the output of the (i + l) -ro element NOT and the first input of the <OR element, the second input of which is connected to the 1st output of the decoder, the inputs of which are connected to the inputs of the control unit, the corresponding outputs of which are connected with the outputs of the second elements And and with the last output of the decoder. 1 1156251