SU907547A1 - Pseudo-random number generator - Google Patents

Description

(5) ALTERNATIVE NUMBER GENERATOR

I

The invention relates to computing and can be used in stochastic computing devices.

A pseudo-random number generator with a uniform distribution is known, which contains a shift register and an absolute modulo two in the feedback circuit.

However, this generator does not allow troubleshooting during its operation l.

The closest technical solution to the invention is a pseudo-random number generator containing a shift register with modulo two adder in a feedback circuit, a decoder, a divider, a delay element, a HE element, the first and second And elements, and a reversible counter, the summing and subtracting inputs of which connected to the outputs of the first and second elements And, respectively, the first inputs of which through the element

delays and a divider are connected to the generator input, and the second inputs to the direct and inverse outputs of the 1st bit of the shift register, the outputs of the shift register are connected to the inputs of the decoder, the output of which is NOT connected to the third input of the first element AND L2.

The disadvantage is the large number of clocks required to determine the presence of a malfunction in the pseudo-random number generator, the large hardware costs for the implementation of the control circuit, the inoperability of the control circuit in the event of a failure resulting in O on the direct and inverse output of the i-mountain. shear.

The purpose of the invention is to simplify the generator circuitry, as well as to increase the speed at fault monitoring and to increase the reliability of the control. The goal is achieved by the fact that in a known pseudo-random number generator, containing shift regis with modulo two in the feedback circuit, a counter, a NOT element, an AND element, an OR element, a delay element, a modulo two adder and a trigger, an output are entered which is connected to the first input of the modulo two adder, the output of which is connected to the first input of the element I, the output of which through the delay element is connected to the counting trigger input the output of the recurrent shift register is connected to the GO by the second input of the modulo adder two, output which is connected to the first input of the OR element, the output of which is connected to the input Counter Reset, the counting input of which is combined with the clock input of the recurrent register of the shift input whose installation is connected to the second input of the OR element and through the element NOT to the second input of the element I. block diagram of the generator. The generator consists of n-bit recurrent shift register 1, to which clock signals are sent from bus clock generator 2 to bus clock 2, which are also input to clock input 3 of counter 4. The generator installation signal is reset to the installation input of shift register 1 and through the element to the input Reset 6 of the counter OR 5 from the input Setting 7 through the element NOT 8, the element I9, the element 10 delay to the counting input of the trigger 11. The output 12 of the last bit of the shift register 1 is connected to the input of the adder 13 modulo two head den the inputs of elements and u9 OR trigger 5. Yield 11 conn chen to an input of the adder 13. The generator operates as follows. The principle of operation control of the generator is based on the property of a pseudo-random sequence that the numbers of the next sequences of signals of the same value (O or 1.) in the series, is removed from the last bit of register 1. It should not exceed the p. In the initial position, register 1 is shifted t in the mode of parallel recording of information, in which 4 the initial number permanently input to the inputs of parallel recording is written to the register (not shown, only one state of the register 00 ... 0 is forbidden). To perform this operation, on and / inu 7 of the installation signal a single level. With the same signal passing through the element OR 5 to the dump bus 6, all bits of the counter k are set to O. Circuit A, consisting of an adder 13 modulo two, element 9, delay element 10, trigger 11, is designed to reset the counter 4 to 0 each time the information value changes on the bus 12. To count the number of the next items O or 1 on the bus 12, the output of the adder 13 modulo two must be in the O. state, which allows the counter to count the number of ticks in a series of signals of one value (say, 0 on the bus 12. Conditions for operation of the counter k are provided that the signals at both inputs of the adder 13 are equal Two. When you change the value of the signal n bus 12 (say from O to 1), at the output of modulator 13 modulo two, a single signal occurs and resets all bits of counter C to O. This same single signal passes through element 9, delay 10 to counting trigger input 11 and positive edge reverts the tri1- ger 11 to the opposite state. The signal changed at the output of the trigger 11, inputted to the input of the adder 13. again restores modulo 13 at the output of the adder 13, allowing the counter k to start counting the number of next signals of another value (say 19 in the series signal removed from counter bus 12. Operation is continued until the next change of the signal on line 12. The magnitude of the delay 10 is selected such that the total delay circuit elements A was sufficient to reset the counter in G. When the power is connected, the trigger 11 is set to an arbitrary state. If this state provides a signal O at the output of the adder 13 which allows the counter to count, then element 9 locks the set signal to the initial state and does not allow trigger 11 to be reset. If the output of adder 13 is set to 1, then And 9 will skip the setup signal to the initial state, which throws the trigger 11 with a positive front and brings the circuit to the ready state.

The occurrence of a malfunction in register 1 causes one or several triggers of this register to be continuously in the same (zero or one states. Continuously shift, this state is less than after n-1 The clock is displayed on the last bit register input. After another n + 1 clock, the control circuit issued a fault condition. Thus, the proposed PRNG detects constant faults through L clock cycles after its occurrence, 2n L, n + 1. The value of L depends on the number of bits of the register 1, in which the malfunction occurred. The maximum value of h-2n occurs when the malfunction is in the first digit of the register 1. For a known device, the malfunction detection time is #, where k is the number of triggers with a counting input, E is the limiting deviation of the number of units to Sequences. The simplification of the generator circuit can be seen from the following: The known device requires the construction of a decoder for n inputs, the cost of which increase in proportion to p. Building a n - input decoder representation

a certain difficulty.

When implementing a device, it is advisable to use shift registers in an integrated design, however these registers do not have inverse outputs, the use of which is provided for in the known invented. Therefore, to realize the generator, a certain number of inverters are required, which is not required in the proposed solution. Since the value of n + 1 (counter module 4 in the proposed solution) is less than the maximum deviation of the number of occurrences of units

(or zeros) in a known device, the counter in the proposed solution has a smaller number of bits than the reversible counter of the known invention. The size of the generator circuit is practically independent of the number of bits of the generated numbers (only the number of digits of the counter increases, equal to, rounded to a large integer number), an increase in n in the known device entails an increase in hardware costs for the implementation of the decoder and increases the number of mounting csj | Zei, which leads to an excess of the cost of production of a known generator compared with the proposed.

Claims (2)

1. US patent number 3700869, class. 235-152, 1972. 2. USSR author's certificate №, cl. G 06 F 1/02, 1977 (prototype).