SU1474853A1 - Parallel-to-serial code converter - Google Patents

Abstract

This invention relates to digital computing. The purpose of the invention is to increase the reliability of the device. To this end, elements 3-6, element 7 with one inverse input, element 15 NOT, element OR 10, two triggers 8.9, counter 12 and decoder 13 are entered into the device containing the shift register 11 and the pulse generator 14. The device converts a n-bit parallel code into a serial one and adds a pilot bit. The first n clock pulses from the output of the pulse generator permit the sequential passage of the bits of the input code to the information output of the device. At the same time, in one of the flip-flops, a check bit is generated, which is outputted by a (P + 1) -th clock pulse. The operation of the device is controlled by a decoder and a counter. 1 il.

Description

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The invention relates to digital computing and can be used in data transmission systems over information channels for a parallel-to-serial code converter.

The purpose of the invention is to increase the reliability of the device. The drawing shows a block diagram of the device.

The device has information inputs 1, control input 2, elements I 3-6, element I 7 with one inverse input, triggers 8 and 9, element OR 10, shift register 11, counter 12, decoder 13, pulse generator 14, the element is NOT 15, informational 16 and controlling 17 outputs of the device.

The device npeofgcheovaniya parallel to the serial code works as follows.

Before starting the triggers 8 and 9 and the counter 12 are in the zero state. The inputs to the device 1 receive an N-bit parallel code. Control input 2 receives a device start signal. This signal, pass through element 5, on

whose second entrance is present

the logical 1 signal from the inverted output of the trigger 9, is fed to the input EWR of the write register 11 shift the starting input of the generator 14 pulses. The pulses from the generator output 14 pulses arrive at the control output 17 of the device. The first pulse trigger 9 is set to the logical 1 state. As a result, logical O is set at the inverse E-input of the shift resolution, and logical 1 is input at the input of the element 6, allowing the clock pulses from the output of the generator 1 pulses to pass through it.

Through the element And 7, on the inverse input of which there is a logical O from the output N of the decoder 13, the clock pulse allows the bits of the converted code from the output of the shift register 11 to pass through the element 3 and, further, through the element 10 to the information output 16 of the device. In this case, in the case of transfer of a single bit, trigger 8 changes its state to the opposite.

0

5 0 5

0 5

An inverse value of the clock pulse from the output of the element NOT 15 adds one to counter 12 and shifts the code in shift register 11. Counter 12 performs the summation of N + 1 pulses. The single signals at the outputs N and N + 1 of the decoder 13 are determined by the corresponding values at the outputs of the counter 12. The number of the outputs of the counter 12 and the inputs of the decoder 13 is determined by the formula

n 1 + Bo “g-2 N.

Claims (1)

A single signal from the output N of the decoder 13 prohibits the passage of clock pulses through element 7 with one inverse input and simultaneously enters the input of element 4. (N, +1) -th clock pulse from the output of generator 14 pulses through element 4 is allowed bit from you-1 trigger 8 to information output 16 of the device. Moreover, to control over an odd or even number of single bits of the transmitted code, the inverse or direct output of the trigger 8 is used, respectively. A single signal from the N + 1 output of the decoder 13 blocks the output of the clock pulses by the generator 14, the triggers 8 and 9 are set and the counter is set 12. The device is again ready for operation. Invention Formula The parallel code 6 conversion unit is serial, containing a shift register, the information inputs of which are information inputs of the device, a decoder, a pulse generator, characterized in that, in order to increase the reliability of the device, a counter, the first and second triggers are entered into it, the NOT element the element OR, the first to the fourth elements And, the element And with one inverse input, and the output of the shift register is connected to the first input of the first element And, the second input of which is connected to the output element AND with one inverse input, and the output - to the first input of the element OR and the first input of the first trigger, the inverse output of which is connected to its second input and the first input of the second element AND, output of which is connected to the second input of the OR element, the output of which is the information output of the device, the control input of which is connected to the first input of the third element AND whose output is connected to the first and second control inputs of the shift register and the trigger start input of the pulse generator, output which is connected to the first inputs of the second trigger and the fourth element I, and the second input of the second element I and is the control output of the device, the inverse and direct output of the second trigger are connected to the second input and third, respectively, 4853 4 and the fourth And elements, the output of the last of which is connected to the direct input of the And element with one inverse input and through the NOT element to the third control input. The shift register and the counter input of the counter, the outputs of which are connected to the corresponding inputs of the decoder, the first the output of which is connected to a third — it is the input of the second element I and the inverse input of the element AND with one inverse input, and the second output is connected to the inputs of the installation of the counter, the first and second triggers and the input of the lock generator of the pulses. ten 15