SU1513626A1 - Series-to-parallel code converter - Google Patents

Description

The invention relates to automation, computing and can be used in information transfer systems. Block 7 controls, by oddness, the output code of the register 8 and trigger 4 after receipt of each bit of information at the input 1, which increases the reliability of the device. The device contains information input 1, input 2 ("Start"), elements 3,6,9, trigger 4, generator 5 pulses, parity control unit 7, shift register 8, control output 10 (Error) and information outputs 11.1 silt

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The invention relates to automation, computing and can

used in transmission systems

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The aim of the invention is to improve the reliability of the device.

The drawing shows a functional diagram of the device for converting a serial code into a parallel one.

The device contains information input 1, input 2 "Start", the first element And 3, the trigger 4, the generator 5 clock pulses, the third element 15 And 6, block 7 parity, the register 8 shift, the second element And 9, the control output 10 (" Error ") and information outputs 11 devices.

The device works as follows:

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Input 2 “Start” receives a pulse signal, which writes “1” to the first digit of shift register 8, and to other bits - “0”, generator 25 5 clock pulses and trigger 4 sets to the initial state. Setting the (n + 1) -th digit of register 8 to the zero state opens element 9, and the pulse signal arriving at input 2 blocks the output of an error signal when changing information at the inputs of control unit 7. After the end of the strobe signal, the enable signals are sent to the first and second inputs of And 6 – 35, and the output 10 of the device produces the result of monitoring the initial state of register 8 and trigger 4. As the pulses are generated, a generator 5 pro 40 records the bits input information to the register 7 and the formation of the control signal at the output of the trigger 4, which supplements the number "1" of information received at the input 1 of the device, to an odd number. When the output element And 9 pulse recording each bit of information in the register 8 is blocked element 6 on the first input, so as not to cause a false error signal 50 when changing information in register 8 and trigger 4. After changing information in register 8 and trigger 4, the result control is set at the output of block 7, and at the end of 55 pulse at the output of the element And 9. The result of the control from the output of block 7 is output to the output 10 of the device. With

an odd number of units of information at the outputs of block 7 is not an error. If the number of units is even, i.e. a failure occurred in register 8 or register 8 failed, then an error signal is output at the device output 10. When receiving input information, the unit previously recorded in the first digit of register 8 will be in (n + 1) -th digit, blocking AND 9 and arriving at output 11 of the device, indicating that the serial code has been converted to parallel.

Thus, block 7 controls, by odd parity, the output code of the register 8 and trigger 4 after arriving at input 1 of each bit of information, which increases the reliability and noise immunity of the device.

Claims (1)

Claim A device for converting a serial code into a parallel one, containing the first element I, the first input of which is the information input of the device, a pulse generator, the output of which is connected to the first input of the second element I, the register whose outputs of the digits are the information outputs of the device, and a trigger And due to the fact that, in order to improve the reliability of the device, a parity check block and a third AND element are entered into it, the second input of the second AND element is connected to the output of the last register bit, the output The second element I is connected to the clock input of the register, the second input of the first element I and the first input of the third element I, the second input of which is combined with the installation inputs of the trigger, register and pulse generator and is the Start input of the device; the output of the first element I is connected to the counting the trigger input, the output of which is connected to the first input of the parity check block, the second inputs and the output of which are respectively connected to the register bits of the same name and connected to the third input of the third element I, the output to torogo uncontrolled output device, an information input of the register connected to the first input of the first element I.