SU1509902A2 - Device for detecting errors in code transmission - Google Patents

Abstract

The invention relates to computing, and can be used in devices for the automated control of transmission nodes and is an improvement of the invention in a.s. N 1091211. The invention, along with control of the output information, provides control of the operability of the elements included in the composition of the device, thus ensuring an increase in the reliability of the control. The device for detecting errors when transmitting codes contains an input register 1, a register 2 check bits, a parallel record control block 3, the first 4 and second 5 modulo control blocks two, a decoder 6, N elements 7 ₁ -7 _N OR and output registers 8 ₁ -8 _{N, N} triggers September ₁ -9 _{N, N} units 10 ₁ -10 _N of the parity control unit 11 generating the error signal error selector 12, the pulse counter 13 and multiplexer unit 14. The selector 12 errors consists of a generator 15 pulses, two elements And 16 and 18, the counter 17 pulses, trigger 19 and the register 20. 1 Cp. f-ly, 1 ill.

Description

The invention relates to computing, can be used in devices for the automated control of transmission nodes and is an improvement of the device according to the author. No. 1091211.

The aim of the invention is to increase the reliability of control by detecting the type of errors.

The drawing shows a functional block diagram of the device.

Device for detecting errors. when transmitting codes, it contains an input register 1, a register 2 control ratios, a parallel record control unit 3, the first 4 and second 5 modulo control units, a decoder 6, OR elements, n output registers 8, -8 ", n flip-flops 9c -9, n blocks 10 /, -10 for parity, block 11 for generating an error signal, selector 12 for errors, counter 13 for pulses, block 14 for multiplexers. The selector 12 errors consists of a generator 15 pulses, the first element And 16, the counter 17 pulses, the second element And 18, the trigger 19 and the register 20.

The device has information input 21, strobe input 22, 23 control bits input, installation input 24, output information output 25, error signal output 26 and device display output 27.

The device works as follows.

In the initial state, the device is set by a signal, at input 24 Reset, when zero information is written to input register 1. In this case, the signal Reset through the block 3 of the control of parallel recording, the elements OR 7, -7and goes to the control inputs of the output registers 8 / - 8 "and the triggers 9i -9, wrapped them. The Reset signal goes to the counter 13 as well, wrapped it, into the control selector 12 at the counter 17, wrapped it, and at the input of the R-flip-flop 19. From the output of the flip-flop 19, the enabling potential goes to the input of the I-16 element. But signals from the generator 15 through element 16 does not pass until an error signal appears at its third input,

The input 21 of the input information, register 1 receives two bytes of information, accompanied by two test bits supplied to the code 23

test bits Information from input 21 from input register 1 and input 23 of control bits of register 2 of control bits is received in registers 1 and 2 by the gate coming from the entrance 22 of the gate. The state of input register 1 is controlled by modulo 2 control units 4 and 5. . Each of blocks 4 and 5 controls one byte of information, with each byte of information being accompanied by its own check bit, which from the register 2 check bits is fed to the corresponding blocks 4 and 5. When information is correctly received, input register 1 at the output of blocks 4 and 5 no error signal. When an error occurs at the outputs of blocks 4 and 5, the error signal is fed to the block 11 to form the error signal and to the inputs of the block 14 of the multiplexers. From the output of the input register 1, the first byte of information arrives I

for informational inputs of output registers 8;, -8. The check bit of the first byte of information from the register 2 check bits goes to the flip-flops 9, -9y and to the block 4 controls modulo two. The second byte of information from the input register 1 enters the control unit 5 via modules two and the decoder 6.

Writing information to the output registers 8-8 and the control bits in the triggers 9-9, can be carried out both sequentially and in parallel when the device is zeroed. Elements lilM 7-7 provide this feature. The decoder 6 is used to control the sequential recording of information from input register 1 into output registers 8 to -8 c, as well as the control bit from register 2 of control bits and flip-flops 9y-9; in accordance with the information received in the second byte. When information is sequentially written, the first, second byte of information, accompanied by a check bit, enters unit 4 of control modulo two and the information inputs of output registers 8 n 8. The second byte of information, accompanied by check bit enters block 5 of control modulo two and to the decoder 6. From one of the excited outputs of the decoder 6, the control signal through the corresponding elements OR 7-7ts comes

5 1

To the control input of one of the output registers 8, -8 and one of the flip-flops 9-9u1, the first byte of information and its check bit are written to one of the output registers and to one of the flip-flops 9, 9j ,. When sequentially writing to each of the output registers

8, -8, and triggers 9 -9, any information may be recorded in any sequence.

When recording information in parallel, the first byte of information and its control bit are recorded in all output registers 8-1 -8f, and in all triggers

9, -9, respectively, by the Reset signal received through the parallel recording control unit 3 through the OR 7 elements (-7f, i to the control inputs of the trigger output registers 9 to 9. The parallel recording of information is applied,

Basically, to zero the device. In this case, all zeros should be written to the input register 1. Both with parallel and sequential recording, information from output registers 8 ;, -8 arrives at outputs 25 of output information. With the output of registers 8, - 8, the information also goes to the inputs of the corresponding blocks 10 (lOf, parity, the second inputs of which receive information from the flip-flops 9, -9 ,. From the outputs of the .10-U blocks, the parity signals arrive at the inputs of the error signal generation unit 11 and at the multiplexer unit 14.

The error signal generation unit 11 generates error signals when information is incorrectly written into the input register, and the failure is determined by comparing the first byte of information and the corresponding bit (check) in control unit 4 modulo two and the second byte and its check bit control unit 5 modulo two. In addition, block 11 generates error signals when writing information to the output register B-8 ", as well as when a malfunction occurs in the output registers by comparing the information present at the output of the corresponding output register 8-8" with the corresponding discharge of the corresponding trigger 9 , -9 and in the corresponding block

101 10j, parity check.

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If an error is detected by the device, the error signal generation unit 11 generates a signal that is output to the device output 26, as well as to the AND element 16 of the control selector 26, allowing the signals from the generator 15 to pass to counters 13 and 17.

The counter 13 provides control of the multiplexer unit 14 by sequentially connecting the output of the multiplexer unit 14 to the outputs of blocks 4 and 5 of the modulo 5 control and the outputs of the 10 10c parity blocks. Moreover, first, modulo two control units 4.5 are polled, and then parity control units 10, -10. When modulated two and 4, and -10, control modules are detected at the output of blocks 4 and 5, the signal for parity of the signal is detected. This signal from the multiplexer output goes through the AND 18 element to the input register-. The country 20 and the register 20 record information that is present at the output from 1 detector 17 and corresponding to the number of the polled signal.

From the output of the register 20, information about the place of failure enters the output 27 of the display. After the first failure is detected, the error signal polling continues until the device is fully monitored. After the termination of the control from the output of the counter 17, a signal is sent to the end of the control, which, entering the trigger 19, sets it to the position prohibiting the passage of pulses from the generator 15, thereby stopping the operation of the selector 12 of the fault. Further operation of the device is possible only after a signal is sent through input 24 to R-input of trigger 19, which, with no information at input 21, reset all output registers 8 ;, -8, and triggers 9 to 9 c as well as counters 13, 17 and trigger 19 .

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Claims (2)

Formula of the invention - 1. A device for detecting errors in the transmission of codes by auth. No. 1091211, characterized in that, in order to increase the reliability of control by detecting the type of errors, an error selector, a pulse counter and a multiplexer unit, are additionally introduced into the device. the output of which is connected to the first input. - the house of the error selector, the first output is 71509 second is connected to the information input of a pulse counter, the output of which is connected to the control input of the multiplexer unit, the first and second information inputs of which are connected to the corresponding outputs of the parity and control units, respectively, two and two eight pulse pulse, the output of which is connected to the first input of the first element AND, the output of which is connected to the first inputs of the pulse counter, the second element H and is the first output of the error selector, the first output of the pulse counter is connected to the first input of the trigger The input of the error selector is connected to Q dinine with the second input of the first element of the signal shaping unit, AND, the second output of the error pulse counter, the input of the control unit is parallel to the first input of the register, and the second output is combined with the third output the input of the error selector, with the selector setting, the output of the second elemental input of the pulse counter and the input AND is connected to the second input of the unit's installation input, the second output of the error selector is the device output output va. 2. The device according to claim 1, which means that the selector 20, the inputs of the pulse counter and the error trigger consists of AND elements, the counters are combined and are the third input of the register, trigger and helium pulses. - Pa, the second input of the second element And is the first input of the selector, the third input of the first element And is the second input of the selector, the second dinene with the second input of the first element AND, the second output of the pulse counter is connected to the first input of the register, the output of which is the second output of the selector, the output of the second element AND is connected to the second input of the register the inputs of the pulse counter and the trigger are combined and are the third input of the selector. Pa, the second input of the second element And is the first input of the selector, the third input of the first element And is the second input of the selector, the second