SU903852A2 - Multi-channel interfacing device - Google Patents

Description

(54) MULTICHANNEL DEVICE FOR PAIRING

one

The invention relates to computing, in particular, to a device for interfacing subscribers with a CRM, and can be used in automated control systems operating in a time-sharing mode.

According to the main author. St. No. 798781 a multichannel interface device is known, containing a group of channels, each of which includes two AND elements and a transceiver amplifier, the working register, the first, second and third inputs of which are connected, respectively, to the first input of the device and the first input of the first element AND, C the output of the first element OR and the first input of the control unit, with the output of the control unit, and the first and second outputs, respectively, with the first output of the device and with the first input of the first element AND of each channel, shift register, input The first is connected to the output of the first element I, a group of outputs to the second inputs of the first and first inputs of the second elements AND of the corresponding channels, and the output to the second input of the control unit, the third, fourth inputs are connected respectively to the second and third inputs of the device, and the second, third and fourth outputs, respectively, with the third inputs of the first elements And channels, with the second input of the first element And, and with the second inputs of the second elements And channels, in each channel the receiving and transmitting amplifier is connected to the output of the first about the element I, output to the third input of the second element I, and input-output to the corresponding input-output from the group of inputs-outputs of the device, inputs

10 of the first element OR are connected to the outputs of the elements AND the corresponding channelsС- /}

The drawback of the device lies in the low reliability of operation, since the absence of control and re-issuance of information to the subscriber when it is distorted results in the output of the device when issuing to the subscriber may distort the transmitted information, which 20 will be detected by the subscriber's tester only after receiving of all bits of information, and according to the malfunction signal generated by it, the digital computer must repeat the exchange.

The purpose of the invention is to increase the reliability of the information produced.

This goal is achieved by introducing a control unit and repeating information output into the device, containing the second, third and fourth elements AND, the second OR element, the failure counter, the control trigger, the lock trigger and the delay element, the input group of the second OR element is connected to the group device inputs and outputs, and through the delay element to the first input of the control trigger, the second input and output of which are connected, respectively, to the output of the second element I, the first input connected to the second output of the working The register and the first input of the third element And, the second and third inputs of which are connected, respectively, to the first and second outputs of the control unit, the first output and input of the blocking trigger are connected, respectively, to the first input and output of the fourth element And, the second input of which is connected to the fifth output of the control unit, the second output of the blocking trigger is connected to the fifth input of the control unit, the second input of the second element AND and the fourth inputs of the first elements AND channels, the input of the fault counter is connected to the output of the third ementa And, the second input of the OR gate and the second input of the lock latch, and an output - to a second output device and the sixth input of the control unit.

FIG. 1 shows a block diagram of the device; in fig. 2 - functional block diagram.

A multichannel interface device consists of an AND 1 element, a shift register 2, an OR 3 element, a control register 4 of the working register 5, channels 6, each of which contains AND 7, AND 8 elements and receiving and transmitting amplifiers 9, input 10-12 and output 13 buses of the device, tires 14 of the group of inputs and outputs of the device for communication with subscribers, block 15 of monitoring and repeating the output of information, output bus 16.

The control and repeat information output unit 15 consists of a control trigger 17, a lock trigger 18, a fault counter 19, AND elements 20, 21 and 22, an OR element 23, a delay element 24. FIG. 1 also indicated the inputs 25-28 and the output 29 of the block 15.

The control unit contains triggers 30 and 31, a pulse counter 32, a pulse generator 33, a control trigger 34, a transmission-reception trigger 35, elements AND 36-43, elements OR 44-46. FIG. 2 also marked tires 47-50, respectively, of the third, fourth inputs of the block 41 and the first input of the block 44.

Element And 1 is designed to control the recording of the address-command at the beginning of the exchange with PVM in the shift register 2, which stores until the end of the exchange the number of channels (subscribers), the sign of the exchange mode (receiving from the digital computer and issuing to the subscriber or issuing to the digital computer

after reception from the subscriber) and other signs received as part of the address command.

The control unit 4 generates the control potentials and shift pulses necessary for organizing the exchange between the digital computer and the subscribers, analyzes the characteristics of the exchange mode after issuing the address-command to the subscriber.

The working register 5 is designed to receive and store the address-commands and information layers coming from the digital computer, issuing them to the subscriber, and operates in a ring register mode, i.e., the information in the output from its output is recorded at its own input. This mode of operation of the working register 5 allows you to save information when it is distorted in channel 6 or in the communication line with the subscriber and to organize the re-issuance of the same information. It also receives and stores information received from the subscriber and outputs it to the digital computer.

Channel 6 is designed to transmit information between the work register 5 and the subscriber, or between the subscriber and the work register.

The unit 15 of monitoring and repeating the issuance of information carries out a random control of the output information at the output of channel 6. When detecting corrupted information, unit 15 generates a potential that blocks channel 6, and then issues control potentials for organizing the re-issuance of information to the subscriber. In case block 15 fixes three distortions after three times issuing the same information to the subscriber, then it generates a “Failure.

The device works as follows.

The exchange with the digital computer always starts at the signal of the operation of the channel, followed by the address-command. The address command is written to working register 5 and to shift register 2. From the working register, the subscriber is always given an address command, which determines his exchange mode. The address command, which stores in register 2, determines the direction that the device exchanges and the number of the exchange channel (subscriber).

When a signal arrives, the operation of the channel via bus 11 to the third input of block 4 from its third output, a resolving potential is output to the input of element I 1. Adreskommanda on syne 10 enters the first

the input of the working register 5 and through the element And 1 to the input of the register 2 shift.

Since the address-command must always be given to the subscriber regardless of the exchange mode, the device in its initial state is always ready for delivery, i.e., block 4 issues

resolving potential at the inputs of the elements And 7 channels 6.

A specific channel is connected by supplying a control potential to the second input of one of the elements AND 7 from the output of the shift register 2.

After receiving the address command via bus 12 from the digital computer, the signal “End of a word. This signal is issued from the digital computer after receiving or issuing each word of information or after issuing an address command. It permits unit 4 to issue shift pulses to the input of the working register. The address command by a serial code from the working register enters channel 6 and through element 7 and the receiving-transmitting amplifier 9 to bus 14 and the communication line with the subscriber.

At the same time, the address command from the output of the working register 5 arrives at the element AND 20, the element OR 23 receives the address command from the input-output transceiver, its amplifier 9. It arrives, and in block 15 the information containing the address in the command is searchable. analyzed. If channel 6 works without distorting the information, block 15 of the inhibitory potential does not output to the inputs of the elements And 7 (in the initial state, the enable potential from the output 29 of block 15 is supplied to these inputs).

If block 15 detects a discrepancy between the information discharged from the working register and the information discharged by the receiving and transmitting amplifier 9, i.e. the information is distorted by channel 6, then it generates a inhibitory potential that goes to the fourth inputs of the And 7 elements of each channel, thereby blocking the further issuance of the address-command (information) to the subscriber. However, information pulses from the output of block 4 continue to flow to the input of the working register. This is necessary in order to restore the original position of the address-command (information) bits in the working register 5. When the last shift pulse arrives from block 4, the information in the working register 5 occupies the initial (initial) state (provided that the number of bits register 5 corresponds to the number of channels). The last shift pulse also arrives at block 15, which, using this signal, removes the inhibitory and outputs the enable potential to the inputs of elements AND 7 of each channel 6. Subsequent shift pulses fed to the input of the working register 5 shift information through element 7 and the transceiver amplifier 9 into the bus 14. At the same time, the transmitted information is being sequentially monitored. If the information is provided without distortion, then block 15 is reset. If the distortion of information repeated, block 15 fixes it, stops further information output to the subscriber, and then organizes the issue again.

The detection of three distortions with a triple repetition of the issuance of the address-command (information) to the subscriber is classified

unit 15 as a malfunction of the device. At the same time, unit 15 generates a "Failure" signal, which is output on output bus 16 in a digital computer and simultaneously in unit 4, in which the output of shift pulses 5 is prohibited. Thus, the cycle and the place of occurrence (channel) of the malfunction is recorded, which reduces the laboriousness of finding and eliminating the malfunction.

Similarly, the output of each word of information is monitored.

0 The trigger 17 of the control remembers bit information received from the second output of the working register 5 and compares it bitwise with the information coming from the input-outputs of the amplifier 9. The lock trigger 18 is intended for temporary

5 of storing the signal of failure and issuing a control potential, the duration of which is determined by the time between the arrival of the failure pulse and the last shift pulse. Counter 19 failures counts count

0 pulse failures (distortion), and upon receipt of the third generates a device failure signal. The delay element 14 delays incoming bit-wise information from the output of the element OR 3, which ensures the steady operation of the trigger 17

5 control.

In the initial state, the trigger 17 outputs the inhibitory potential at the input of the element And 21, and the blocking trigger 18 outputs the permitting potential to the output bar 29

g and the input element And 20, and prohibiting - to the input element And 22. On the input bus 26 enters the resolving potential (the mode of reception from the digital computer and the issuance to the subscriber).

When issuing to the subscriber, it can be an address-command, information is bit by bit

5 comes from the output of the working register through the element 20 and to the input of the trigger 17 of the control. Each impulse arriving on the splint 25 and corresponding to the transmission of one bit of information sets Frigger 17 to the opposite state. The pulse is the same, but from the input-output amplifier 9 through

the element OR 23 and the element 24 delay

arrives at the first input of the trigger- 17 and

sets it back to its original state.

The shift pulses, which are received by the switch5 not 27 to the input of the element 21, do not pass to its output, since the trigger 17 outputs the resolving potential after the shift pulse and removes it before the next shift pulse arrives. Similarly, each output bit is monitored.

0 information.

If the input of the trigger 17 on the bus 25 receives a pulse of information (it sets the trigger 17 in the opposite state), and the output of the receiving and transmitting amplifier 9 and, respectively, at the input of the element OR 23 it is absent (the element And 7 is faulty, the amplifier 9 of the channel 6 or its communication lines), then the trigger 17 remains

in the opposite state, and from its output a permitting potential is input to the input of the element 21.

A shift impulse coming along the splint 27 passes through the element AND 21, which is opened by the resolving potential on the splint 26, to the input of the trigger 18 of the element OR 23 and the counter 19 of failures. The trigger 18 is set in the opposite state and sends a suppressive potential through the bus 29 to the input of the element AND 20, which enters block 4 and to the inputs of the elements 7 of each channel 6, thereby blocking further output of information to the subscriber. The shift pulse from the output of the element 21 through the element OR 23 and the element 24 of the delay trigger 17 is set to its initial state and the counter 19 detects the first failure. Block 4 continues to produce shear pulses. The last shift pulse, corresponding to the output of the last bit of information, enters through the bus 28 through the element 22 and sets the trigger 18 to the initial state. From the first output of the trigger 18 to the input of the element And 22, the inhibitory potential is output, and through the bus 29 to the input of the control unit 4 and to the elements And 7 of the channels 6 - the enabling potential.

The information, having saved from the work register, is again issued to the subscriber. If the output of this information is carried out without a fault, then the counter 19 is reset to the initial state by the signal of the end of the output of the word of information (this link is not shown).

When a fault (distortion) is detected in the repeated information output, unit 15 operates in the same way, and a second failure is detected on counter 19. If a failure (distortion) is detected and at the third issue to the subscriber (the first two fails are considered random) of the same information, then the counter 19 outputs a device failure signal to the bus 16. This signal is output in the digital computer and in block 4, in which the generation of shift pulses stops.

In block 4 of control (Fig. 2), trigger 30 is designed to issue a permit potential only at the time of reception of the address command, at the rest of the exchange time it outputs a inhibitory potential. The trigger 31 is used only in the mode of receiving information from the subscriber and issuing it to the digital computer. Pulse counter 32 counts the shift pulses when information is output to the subscriber and when information is received from the subscriber, and generates overflow pulses when the last shift pulse arrives. The control trigger 34 is designed to control the issuance of clock pulses from the generator 33 output. The receive / output trigger 35 provides device exchange modes: if the enabling potential on bus 26 is received from the digital computer and outputs information to the subscriber; if the resolving potential on bus 48 is the output to the digital computer of information received from the subscriber. The control unit 4 operates as follows.

At the beginning of the exchange on the input 11

From the digital computer, a signal is received that indicates the operation of the channel, which sets the trigger 30 to the opposite state, at which the resolving potential along the busbar 47 is output from its output.

After receiving the address command via the input 12 bus, the signal "End of a word" is received from the CWC, which sets the trigger 30 to its initial state, i.e., from its output, a blocking potential is given via bus 47. Simultaneously, the signal "The end of the word arrives at the first input of the element 36,

which is opened by the resolving potential from the output of the trigger 35. From the output of the AND 36 signal, the signal through the element OR 45 enters the input of the trigger 34 and sets it in the opposite state. The resolving potential from the output of the trigger 34 is fed to the input of the element And 37. The frequency from the output of the generator 33 through the element And 37 enters the busbar 27 (shift pulses in the working register) and through the element OR 44 to the input of the counter 32. Overflow pulse

 from the output of the counter 32 through the element And 39, open at the resolution potentials from the output of the trigger 35 and from the bus 29 (the element 38 is closed at this time by the inhibitory potential from the output of the trigger 35), and the element OR 46 is fed to the input of the trigger 34. From its the output of the element And 37 is given a inhibitory potential, i.e., the generation of shift pulses is prohibited.

At the same time the signal from the output of the element And 39 is fed to the inputs of the elements And 40

5 and 41, where the exchange mode analysis is performed: the control potential of the output mode is supplied to the other input of the element 40 and the control potential of the reception mode to the other input of the element 41.

° This mode of operation is subject to the issuance of the address-command without failure. If a failure occurs, then a barring potential flows through bus 29, which prohibits the passage of the last pulse.

5 to the output of the element 38 and further to the analysis of the exchange mode and the setting of the trigger 34 to the initial state.

In the event of a faulty situation, the generation of shear pulses does not stop, and they continue to flow along the busbar 27 to the input

Claims (1)

0 working register and through the element OR 44 to the input of the counter 32. This is necessary in order to restore to the working register 5 the original position of the address-command bit. After the last shift pulse has been received, the address-command takes the initial position in the working register, i.e. the first bit of the address-command is placed in the first bit of the 5th register, respectively, the second in the second and so on. At the same time, the last shift pulse is output counter 32, as a signal for its overflow (with the same signal, counter 32 is reset), which via bus 28 enters block 15 for initialization of lockout trigger 18. The overflow pulse of the counter 32 through the elements 38 and 38 does not pass, since they are closed by the inhibitory potentials, respectively, from the output of the trigger 35 and the bus 29. When the block 15 detects a second failure during the re-issuance of the address command to the subscriber, the block 4 works in a similar way. When a third failure is detected from block 15, the bus 16 receives the “Failure” signal, which sets the trigger 34 to its initial position through the OR 46 element. From the output of the trigger 34 to the element I 37, the inhibitory potential enters, thereby stopping the output of the shift pulses along the busbar 27 to the working register 5. Thus, the analysis of the exchange mode is performed only after the correct issuance of the address command to the subscriber. The operation of the control unit proceeds in a similar way when issuing information to the subscriber. A feature of the control unit is as follows. The overflow pulse developed by the counter of 32 pulses (in case of detection of distortion of the output information by the block 15) does not pass through the AND 39 element, since it is closed by the inhibitory potential from the output of the blocking trigger 18. This means that the control trigger 34 is not reset (via the element AND 39 and the element OR 46) and does not indicate the inhibitory potential at the input of the element 37, i.e., across the bus 27, the shift pulses continue to flow into the working register. In the fault detection (failure) mode, the overflow pulse arrives through the bus 28 only in block 15 and sets the lock trigger 18 to its initial state. The device is prepared for re-issuing information. Thus, the proposed device provides control of the output information and re-issue it, which increases the reliability of the work. In addition, the device fixes the moment of failure and failure of channels and communications equipment of subscribers, which ultimately increases the reliability of the system in which the device is used. Claims of the Invention Multi-channel interface for aut. St. No. 798781, characterized in that, in order to increase the reliability of the output information, a control and repeat information output block is inserted into the device, containing the second, third and fourth AND elements, the second OR element, the counter of failures, the control trigger, the blocking trigger and the delay element, the group of inputs of the second element OR is connected to the group of inputs and outputs of the device, and the output through a delay element to the first input of the control trigger, the second input and output of which are connected, respectively, to the output of the second element AND, first input connected to the second output of the working register, and with the first input of the third element And, the second and third inputs of which are connected, respectively, to the first and second outputs of the control unit, the first output and input of the lock trigger are connected, respectively, to the first input and output of the fourth element And, the second input of which is connected to the fifth output of the control unit, the second output of the lock trigger is connected to the fifth input of the control unit, the second input of the second element AND and the fourth inputs of the first elements AND channels , the input of the fault counter is connected to the output of the third element AND, the input of the second element OR and the second input of the blocking trigger, and the output to the second output of the device and the common input of the control unit. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 798781, cl. G 06 F 3/04, 1979 (prototype). FIG. 2