SU1058070A1 - Scaling device - Google Patents

Description

The invention relates to the field of pulsed technology and can be used in automatic control devices, as well as in computer equipment devices.

A predetermined counter is known, a tact block power supply unit, whose pitch input is connected to the input of the counting unit, a comparison element, the installation inputs of which are connected to the outputs of the counting unit, and the control inputs are connected to the output of the master unit and to the BTOpcBvi input of the unit, clock feed, valves and delay nodes, the output of the comparison element is connected to the first valve inputs, the outputs of which are connected to the second inputs of the subsequent valves and to the third l yuschim zgschgioschego input unit inputs a extra delay units are connected to a first input of a clock supply unit 1.

The disadvantage of this device is low. The reliability of its operation, since it is performed in an unreliable version, because the device scheme does not contain majoritarian and backup elements, as well as elements that allow the device to self-monitor the device for operation before each operation cycle of the device.

A scaling device is known, it contains an input bus, a self-checking bus, a group of information buses, a holding block, a counting block, a comparison block, a shift register, a block of OR elements, three OR elements, five AND elements, a delay element and a trigger, direct and inverse the outputs of which are connected respectively to the first inputs of the first and second elements I and respectively to the first inputs of the third and fourth elements I, the second inputs of which are connected respectively to the input bus and to the self-test bus, outputs of the third and fourth The AND elements are connected to the inputs of the first OR element, the output of which is connected to the counting input of the counting unit and the gate input of the comparison unit, the first group of inputs of which is connected to the outputs of the counting unit, the output of the comparison unit is connected to the second inputs of the second and first elements AND, the output of the last from which is connected to the first input of the second OR element, the output of which is connected to the control input of the task block, the inputs and outputs of which are connected respectively to the group of information shim and the first group of The output of the OR block whose outputs are connected to the second group of inputs of the comparison block, the second input of the second OR element is connected to the first input of the third OR element, to the output of the fifth AND element and to the d input of the trigger, the outputs of the first and second AND elements are connected respectively to the second input of the third element OR and the clock input of the shift register, the outputs of which are connected to the second group of inputs of the block of elements OR, the additional output of the shift register is connected to the first input of the fifth element And, the second input of which It is connected with the output of the most significant bit of the counting unit, the reset input of which is connected through a delay element and with the output of the third element OR 2.

A disadvantage of the known device is that it does not provide full control on the operability of the entire device, since only partial control is provided on the performance of the comparison unit, namely from the available, for example 1024 combinations of time exposures formed by a 10-bit counting unit Only 10 exposures are monitored, which represents 10% of the possible number of COPs for the master block. In addition, the known device in the process of monitoring does not carry out a signal about the malfunction of the device, which does not allow promptly judging the efficiency of the device.

The purpose of the invention is to increase the reliability of the device.

This goal is achieved by the fact that in a scaler containing an input bus, a self-test bus, a group of information buses, a driver unit, the first counting unit, a comparison unit, a block of OR elements, three OR elements, five AND elements, a delay element, and the first trigger, the direct and inverse outputs of which are connected respectively to the first inputs of the first and second elements AND, respectively, to the first inputs of the third and fourth elements AND, the second inputs of which are connected respectively to the input bus and the self-test bus, moves the third and fourth members are connected to the inputs of AND | «IDN first element, whose output is connected to the counting input of the first counting unit and the comparing unit strobirukntsim input, the first input group connected; with the outputs of the first counting unit, the output of the comparison unit is connected to the final inputs of the second and first elements AND, the output of the last one of the CSO; 4) connected to the first input of the second OR element, the output of which is connected to the control input of the unit, the inputs and outputs of which are connected respectively to the group of information buses and to the first group of inputs of the block of elements OR, the outputs of which are connected to the second group of inputs of the comparison unit ., the second input of the second element OR is connected to the output of the fifth element AND and with the clock input of the first trigger, the second counting unit, the second trigger and the sixth element are entered and the first and second inputs of which are connected respectively to The additional output of the first counting unit and with the inverse output of the first trigger, the output of the second element I is connected to the counting input of the second counting unit, the outputs of which are connected to the second group of inputs of the unit; go OR; the auxiliary output of the second counting unit is connected to the first inputs of the fifth element And the third element OR, the second input of which is connected to the second input of the fifth element AND and to the output of the sixth element AND, the inverse output, the clock input and the input setting to zero the second trigger are connected respectively with the third input of the fourth element AND, with the output of the third OR element and with the output of the delay element, the input of which is connected to the output of the fifth element AND,

In the drawing, a functional diagram of the counting device is described.

The scheme contains counting blocks 1-1 and 1-2, block 2 of comparison, dropping block 3, block 4 of elements OR, elements OR 5-1 - 5-4 of block 4, triggers 6-1 and .6-2, elements AND 7-1 - 7-6, elements OR 8-1 - 8-3, delay element 9, bus 10 self-test, input bus 11, group 12 information 11ShN, output tires 13-15.

Entry error 11 and tire. 10 CciMono-checks are connected respectively to the first inputs of the And 7-4 and 7-3 elements, the second inputs of which are connected: respectively to the inverse and prjfim outputs of the trigger 6-1 and respectively to the first inputs of the And 7-1 and 7-2 elements, the outputs of which are connected respectively, with a counting input of a counting unit 1-2 and with the first input of the SHSh 8-1 element, the second input of which is connected to the input of the delay element 9, with the clock input of the trigger 6-1 and with the output of the AND 7-5 element. The first input element And 7-5 is connected to the first input of the element OR 8-3 and with the output of the element And 7-6, the first A input of which is connected to the first input of the element And 7-1, the second VCH which is connected to the second input of the element And 7-2 and with the output of the unit 2 of comparison, the first and second groups of inputs cat: h; They are connected respectively to the outputs of the counting unit 1 and to the outputs of the elements OR 5-1 to 5-4 blocks 4. The first inputs of the elements OR 5-1 to 5-4 blocks 4 are connected to the outputs of the master block

3, the inputs of which are connected to a group of 12 information buses. The control input of the master unit 3 is connected to the output of the element OR 8-1, the second inputs of the elements OR 5-1 to 5-4 of the block 4 are connected to the outputs of the counting unit 1-2, the auxiliary output of which is connected to the second inputs of the element 7 7 and element OR 8-3, the output of which is connected to the clock input of the trigger 6-2, the installation input to zero and the inverse output of which are connected respectively to the output of the delay element 9 and the third input of the AND 7-3 element, which is connected to the second input of the OR element 8- 2, the output of which is connected to the gating input of the unit 2 of the comparison and with the counting input of the counting unit 1, the auxiliary output of which is connected to the second input of the And 7-6 element, the output buses 13-15 are connected respectively to the output of the And 7-2 element and to the direct outputs of the flip-flops 6-1 and 6-2.

The decisive block 3 consists of n receive registers made on RS flip-flops, the single outputs of which are connected bitwise to the first input of the output elements AND, combined into groups respectively of the receiving registers, and the second inputs of the output elements AND of each group are connected between each other and connected to the corresponding outputs of the ring shift of its register, and the outputs of the same output elements AND of each group are connected to the inputs of the corresponding OR elements, the outputs of which are connected to the outputs of the master unit 3 s-inputs RS-flip-flops. receiving registers are connected to the outputs of the input elements And, combined into groups, respectively, the receiving registers. The first inputs of the input elements And of each group are interconnected and connected to the corresponding outputs of the annular shift register, and the second, the inputs of the same input elements And the group of signals are interconnected and connected to the corresponding information input of block 3 (n-1-1) th info1 whose input input is connected to the third inputs of the input elements AND and to the first input of the additional element OR, the second input of which is connected to the control input of the back of unit 3. and the output of the additional element One or connected to an input of serial shift ring sdvigakitsego Regis formed on the JK-flip-flops.

The device works as follows.

Before the start of operation, the schegla of the proposed device is brought to its original state, as a result of which the fourth blocks 1-1 and 1-2, the triggers 6-1 and 6-2, the receiving registers of the master unit 3 are in the initial fieBOM state, and in the first bit of the ring shift register of master block 3, one is recorded. Then, over the lines of communication from the information transmission channel, over the information buses of group 12 to the driver unit 3, recording of information words is recorded, followed by gating pulses arriving via (information signal from group 12 to receive on device bus 13 The master block 3 on the leading edge of the strobe pulse, coming through the (n + 1) -th data bus from group 12, writes the first information word to the first receiving register, since the signal from the output of the first bit The first group of input elements was prepared for operation. The outputs of which are connected to the S inputs of the first receiving register, and the falling edge of the strobe pulse shifts the unit to the second bit of the ring shift register. As a result, the second group of input elements And, the outputs of which are connected to the S-inputs of the second receiver register.Then, along the information buses of group 12, the second information word enters the backward block 3, followed by a strobe by the impulse impulse arriving on the (n + 1) information bus of group 12. The recording of the second and subsequent information words into the second and subsequent reception registers is similar to the previously described cycle. After writing the nth information word in the ring shift register, the unit is shifted by () bit. As a result, none of the receiving registers in which the recorded information words are stored are connected to the outputs of the master block 3. Therefore, there are no control signals at the outputs of the master block 3. The operation of the proposed device begins with a self-test mode, which performs a self-check on the operability of both the first counting unit 1-1 and the comparison unit 2. To do this, the self-test bus 10 receives impulses with a following frequency equal to or very large: The target operating frequency of the device arrives through the bus 11 of the operating frequency of the device. This allows the device to self-check for minimized time. Since the triggers 6-1 and 6-2 are found in the initial zero state, elements 7-1, 7-3, and 7-4 are prepared for operation. This ensures the passage of pulses coming through the bus 10 of the device self-test through the AND 7-3 element and the OR 8-2 element to the counting input of the counting unit 1-1, performed on the EC triggers, which switch to the opposite state on the falling edge of the input pulse. carried out the registration of input pulses in the counting unit 1-1. Because. the counting unit 1-2, performed on the ZK-triggers, is in the initial zero state, and the outputs of its block 3 also lack control signals, and there are no control signals at the outputs of the elements OR 5-1-5-4-4 of block 4 which corresponds to the choice on the second group of inputs, block 2, the comparison of the zero number. On the first group of inputs of block 2 in comparison with the n outputs of the counting block 1-D, the zero information also arrives. This ensures that the unit 2 is prepared for comparing the zero output at its output, and when the first 11 impulse arrives at the device self-test bus 10 through element 7-3 and element 8-2 at the gate input of the comparing unit 2, at the output of the comparing unit 2 a pulse appears, which through element 7-1 enters the input of the counting unit 1-2. On the falling edge of this pulse, the counting unit 1-2, registering it, switches the first counting bit to one, forming a number on the n outputs containing a unit in the lower counting range; This number through the elements OR 5-1 - 5-4 of the block 4 is fed to the second group of inputs of the block 2 of the comparison. The counting unit 1-1 registers the first counting bit to the unit state by the falling edge of the first pulse arriving on the bus 10 of the device’s self-test, registering a number containing one in the least significant bit on n outputs. This number goes to the first group of inputs of unit 2 of the comparison,. preparing it for work. Upon arrival, a second pulse arriving via the bus 10 of the device self-test at the gate input of the comparator unit 2, at the output of the comparator unit 2 an impulse appears, which through the AND 7-1 element enters the input of the counting unit 1-2. On the falling edge of this pulse, the counting unit 1-2, registering with it, switches the first counting bit to the zero state, and the second counted bit — into the single state, forming a number in the second counting raz de. This number is through the elements 5-1 - 5-4 logical block

It appears on the second group of inputs, Lok 2 Comparison.

The counting unit 1-1 registers the first counting bit to the zero state on the falling edge of the second self-test device inu 10, registers it, and the second counting bit in the unit state, forming a number on the n outputs containing one . in. the second countable bit de. This number arrives at 10 the first group of inputs of block 2 compare, preparing it for work.

The reception of the third and subsequent pulses coming through the bus 10 from testing the device is similar to the described cycle.

Upon reaching the counting blocks 1-1 and 1-2 of the unit state in all the counting bits, the comparison block 2 is once again prepared for operation. On the front of the next pulse coming through the bus. 10 self-test device, optional. The (n + 1) th overflow output of the counting unit .1-1 and at the output of the comparison unit 2 pulses are generated. On the leading edge of the pulse arriving through element 7-1 at the counting input of the counting unit 1-2, the counting unit 1-2 at the additional (n + 1) th overflow output forms a pulse. On the falling edge of the pulses arriving at the counting inputs of the counting blocks 1-1 and 1-2, the blocks 1-1 and 1-2 are switched to the initial zero state. 35

The overflow pulse from the counting unit 1-1 through element 7-6 goes to one of the inputs of the element 7-5, to the other input of which an overflow pulse comes from the counting 40 block 1-2. By coincidence of these pulses, the element 7-5 Forms at the output a pulse, on the falling front of which the trigger 6-1 switches to one state, blocking the operation of elements 7-1, 7-3 and 7-6 and preparing elements 7-2 for operation and 7-4, and also form the Ready signal on the device bus 14.

The pulse from the output of the element 7-5 through the delay element 9 is fed to the H input of the trigger 6-2 to the C input of which is fed through the OR element 8-3 pulses. From the overflow outputs of the counting blocks 1-1 and 1-2. Since the flip-flop 6-2 switches to the single 55 state on the falling edge of the pulse, which is sent to the input C, t in this case it will remain in the zero state, because the pulse arriving at the input R holds it 60 in the zero state.

On the falling edge of the pulse coming from the output of element 7-5 to j, the main input of the master block 3 is shifted by one from 65

(n + 1) -th bit in the first bit in the ring shift register of the driver block 3. As a result, the first receiver register in which the first information word is stored is connected to the outputs of the driver block 3. This information word through the elements OR 5-1 to 5-4 of block 4 is fed to the second group of inputs of block 2 of the comparison.

This self-test mode ends and starts the operating mode of the device.

In case of a mismatch of the operation of the counting blocks 1-1 and 1-2 in the device self-test mode, the pulses at the overflow outputs of the counting blocks 1-1 and 1-2 do not appear simultaneously. As a result, the element 7-5 does not produce, - at the output impulse, which through the delay element 9 would arrive at the H-input of the trigger 6-2. Therefore, the trigger 6-2 on the falling edge of the pulse, coming from the overflow output of one of the counting blocks 1-1 or 1-2 through the OR element 8-2 to the C input, switches to one state, prohibiting the operation of the element 7-3 and forming signal There is no norm on the bus 15 device. After this operation, the device is terminated.

Thus, in the process of conducting a self-test mode of operation of the device, full self-control is carried out on the operability of the counting unit 1-1 and the comparison unit 2. In the event of a malfunction in the counting unit 1-1 or unit 2 of the comparison, in the self-test mode of the device operation, a No signal is issued by the device, indicating a device malfunction, and further operation of the device is prohibited.

When the device operates in the operating mode, the operating frequency of the input pulses, coming through the bus 11, the operating frequency of the device through the AND 7-4 element and the OR 8 element enters the counting input of the counting unit 1-1. The counting bits of the counting unit 1-1 begin to fill in and, on reaching the counting unit 1-1, the value of the first information word coming from the outputs of the master block 3 through the elements OR, 5-1 to 5-4 block 4 to the second group of inputs of block 2 comparison, the comparison unit 2 is prepared for operation. Upon the arrival of the next input pulse to the building input of the comparator unit 2, an impulse is formed at the output of the comparator unit 2, which is fed through the AND 7-2 element to the device bus 13, and j through the OR element 8-1 to the pack-. the equal input of the master unit 3, which is on the trailing edge of the pulse

Claims (1)

A CALCULATING DEVICE containing an input bus, a self-test bus, a group of information buses, a master unit, a first counting unit ”, a comparison unit, a block of OR elements, three OR elements, five AND elements, a delay element and a first trigger, the direct and inverse outputs of which are connected respectively, with the first inputs of the first and second elements. Comrade And and accordingly with the first inputs of the third and fourth elements And, the second inputs of which are connected respectively to the input bus and the self-test bus, the outputs of the third and fourth elements And are connected to the inputs of the first element. that OR, the output of which is connected to the counting input of the first counting unit and the gate input of the comparison unit, the first group of inputs is connected to the outputs of the first counting unit, the output of the comparison unit is connected to the second inputs of the second and first elements AND, the output of the last of which is connected with the first input of the second OR element, the output of which is connected to the control input of the master unit, the inputs and outputs of which are connected, respectively, with a troupe of information buses and with the first group of inputs of the block of OR elements, the outputs of which th second group are connected to the inputs of the comparator, the second input of the second OR gate coupled to an output of the fifth AND gate and to the clock input of the first flip-flop, wherein. That, • in order to increase the reliability of operation, a second counting unit, a second trigger and a sixth element And, the first and second inputs of which are connected respectively to the additional output of the first, counting unit and the inverse output of the first trigger, are introduced into it, the output of the second element And is connected to the counting input of the second counting unit, the output of which is connected to the second group of inputs of the block of OR elements, the additional output of the second counting block is connected to the first inputs of the fifth AND element and the third OR element, the second input of which connected to the second input of the fifth element And with the output of the sixth element And, inverse.- _ output, clock input and input set-. ki to zero of the second trigger are connected. respectively, with the third input of the fourth AND element, with the output of the third OR element and with the output of the delay element ', the input of which is connected to the output of the fifth element I. & >