SU1368981A1 - Counter - Google Patents

Description

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The invention relates to a pulse technique and can be used in automatic control devices, as well as in computing devices.

The aim of the invention is to increase reliability.

The goal is achieved by introducing new constructive features.

The drawing shows a functional diagram of the counting device.

The counting device contains the first, second counting blocks 1.1 and 1.2, the first, the second blocks 2.1 and 2.2 of the comparison, the master block 3, the switch L, the first, second, third 1K-trigger 5.1-5.3 RS-flip-flop 6, the multi-purpose element 7 digital structures, the first, second, third and fourth two input elements And 8.1-8.4, the first, second and third three-input elements And 9.1-9.3 first and second many

input elements OR 10.1-10.2, first 25 three-input elements AND 9.1 and 9.2,

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input element OR 11.1 is connected to the clock input of the first IK-5.1 trigger and to the R-input of the second 1K-trigger 5.2, the direct output of which is connected to one of the inputs of the third two-input element AND 8.3, the outputs of the first counting unit are connected to the installation inputs of the first block 2.1 comparison, the outputs of the master unit 3 are connected to the control inputs of the second comparison unit 2.2 and to the second group of information inputs of the switch 4, the outputs of which are connected to the control inputs of the first comparison unit 2.1, the outputs of the second counting unit 1.2 Keys to the mounting block inputs of the second comparator 2.2, starter bus 13 is connected to the input of the pulse generator 12, whose first output is connected to counting inputs of said first and second counting units 1.1 and 1.2, the first inputs of the first and second

second, third, fourth two-input elements OR 11.1-11.4, generator 12 pulses, start bus 13, information inputs 14 of the driver unit, device output 15, outputs 16 and 17 for the indication of the first and g channels, and the first the counting unit 1.1 is connected to the first group of information inputs of the switch 4 and to the inputs of the multipurpose element 7 of the digital structures, the odd outputs of KOTopoi o are connected to the inputs of the first multi-input element OR 10.1, and the even outputs - to the inputs of the second multi-input element OR 10.2, the output of the first multiple input New element OR 10.1 is connected to one of the inputs of the first two-input element AND 8.1, the output of which is connected to one of the inputs of the first two-input element OR 11.1 and with the 1-input of the first 1K-trigger 5.1, the inverse output of which is connected to the second input of the first two-input element AND 8.1 , the output of the second multi-input element OR 10.2 is connected to the first input of the second two-input element AND 8.2, the output of which is connected to the second input of the first two-input element OR 11.1 and to the K input of the first 1K-trigger 5.1, which direct output li ne to a second input of the second two-input AND gate 8.2, the output of the first dvuh5

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with the first input of the fourth two-input element AND 8.4 and one of the inputs of the second two-input element OR 11.2, the second output of the generator 12 pulses are connected to the first input of the third three-input element AND 9.3 with I and the clock inputs of the second 1K flip-flop, with the second input of the third two-input element AND 8.3, the output of the second two-input element OR 11.2 is connected to the clock input of the third 1K-flip-flop 5.3, whose direct output is connected to the control input of the switch 4 and to the second input of the fourth two-input element And 8.4, the third output th element dvuhvhrdovogo 8.3 and connected to the first input of the third two-input OR gate 8.3, the second input of which is connected to the output of the fourth two-input AND gate 8.4 and the output of the third two-input OR gate 11.3 is connected to S-input of RS-flip-flop 6, straight

0 whose output is connected to the second input of the second three-input element And 9.2, the output of the first comparison block 2.1 is connected to the second inputs of the first and third three-input

5 elements And 9.1 and 9.3, the third inputs of which are connected to the inverse output of RS-flip-flop 6 and connected to the K-input of the second 1K-flip-flop 5.2, the output of the third three-input element

This AND 9.3 is connected to the second input of the second two-input element OR 11.2, the output of the first three-input element AND 9.1 is connected to the first input of the fourth two-input element OR 11.4, the second input of which is connected to the output of the second three-input element And 9.2, the third input of which is connected to the output of the second the comparison unit, the output of the fourth two-input element OR 11.4 is connected to the control input of the master unit 3.

The master unit 3 consists of p-receiver registers made on RS-flip-flops, the unit outputs of which are bit-wise connected to the first inputs of output elements AND, combined into groups of receiving registers respectively, and the second inputs of output elements AND of each group are interconnected and connected to the corresponding outputs of the annular shift register, and the outputs of the same output elements AND of each group are connected to the inputs of each of the corresponding OR elements, the outputs of which are connected to the outputs of the master unit 3. S-inputs RS-flip-flops receiving registers are connected to the outputs of the input elements And, combined into groups, respectively, the receiving registers. The first inputs of the input elements AND of each group are interconnected and connected to the corresponding outputs of the annular shift register, and the second inputs of the same input elements AND of each group are interconnected and connected to the corresponding information input of the master block 3, (n + 1) -th the information input of which is connected to the third inputs of the input elements AND and to the first input of the additional element OR, the second input of which is connected to the control input of the master block 3, and the output the additional element gShI connected to the input of serial shift circular shift register formed on the 1K-trig- erah.

Switch 4 contains the first group of input elements I, the first inputs of which are respectively connected to the information inputs of the first group of switch 4, the second group of information inputs of which are connected to the first inputs of the second group of input elements I, respectively, and the control input of the switch 4 is connected to the second inputs of the elements of the first group and with the input of the element NOT, the output of which is connected to the second inputs of the second group of elements AND, the outputs of the elements of the same name AND the first and second groups are connected to the first second inputs of the corresponding element or the group, the outputs of which are respectively connected to the outputs of the switch element 4. 5 7 Multipurpose digital structures (METSS) consists of n differential amplifiers, transistors formed on mnogoemitternyh integrally. Upon arrival 0 of the input pulse of long duration, the MECS generates a pulse of small duration at the output.

The device works as follows.

5 Before the start of the operation of the proposed device, the circuit is reset. As a result, the counting blocks 1.1 and 1.2 and 1K flip-flop 5.1-5.3, RS-flip-flop 6, the receiving 0 registers of the master block 3 are in the initial, zero state, and for the first bit of the ring shift register of the master block 3 are written unit.

Then, via the communication lines from the information transmission channel, the information inputs 14 of the master unit 3 write to the master unit 3 and n information words, followed by a gating pulse, which enters the (n + 1) -th information input 14 of the master unit 3 , to obtain the output of the device 15 given numbers. The master unit 3, at the 5th leading edge of the strobe pulse, which arrives at the (n + 1) -th information input 14, writes the first information word, arriving at the information input Q 14, into the first receiving register, since the output signal the first bit of the annular shift of the register is prepared for work the first group of input elements I, g outputs of which are connected to the S-inputs of the first receiving register. Along the trailing edge of the gating pulse, the unit is shifted to the second discharge of the ring, shifting 5

register. As a result, the second group of input elements AND is prepared for operation, the outputs of which are connected to the S-inputs of the second receiving register. Then the information inputs of the p-assigning unit 3 receives the second information word, followed by a gating pulse, arriving at the (n + 1) -th information input. Writing the second and subsequent information words to the second and subsequent reception registers is similar to the previously described cycle. After writing the nth information word, the ring, shift register is again in its initial state, i.e. in the first discharge of the ring, shift register, a unit is recorded that connects to the first inputs of the elements OR the first group of output elements AND connected by one of the inputs to the outputs of the first receiving register

Thus, after the information words are written to the master block 3 n, the first information word appears on the outputs of the master block 3, which arrives at the control inputs of the second comparison block 2.2 and on the data inputs of the second group of the switch.

After setting the information words to the driver unit 3, the device is ready for operation.

Then, the start-up signal arrives at the start-up pin 13, in which the pulse generator 12 begins to produce at its outputs T and T two sequences of pulses with a duty ratio Q greater than 2 shifted relative to each other by 1/2 period. The pulse frequency at the outputs of the pulse generator 12 is determined by the required accuracy of the time stamping into the automatic control system.

The pulses from the output T, the generator 1 of the pulses arrive at the counting inputs of the first and second counting blocks 1.1 and 1.2, which begin to fill with the pulses. And upon the arrival of the falling edge of the next pulse corresponding to the final value of the value of the first information word set at the control inputs of the first comparison unit 2.1 through the switch 4, the outputs of the first counting section 1.1 are set

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New informational word. This word enters the installation inputs of the first comparison unit 2.1, where it is compared with the first information word coming from the outputs of the master unit 3 via the second group of information inputs of the switch 4 to the control inputs of the first comparison unit 2.1.

Consider the operation of the switch in the main mode, when information arrives at the outputs of the switch 4 with

the second information group and the process of connecting the first group of information inputs of the switch 4 to its outputs.

As a result of comparing codes on

the control and installation inputs of the first comparator unit 2.1. A signal is generated at its output, which is present during one period of the input signals coming from the output T of the pulse generator 12. This signal, which is probed by the next pulse from the output T of the generator 12 pulses at the three-input element AND 9.1, goes through the fourth two-input element OR 11.4 to the device code 15 and to the control input of the master unit 3, which em on the outputs of the second information word.

Upon the arrival of successive pulses from the output T, the generator of 12 pulses, the counting blocks 1.1 and 1.2 continue to fill, switching to the next position along the falling edge of the input pulses, and upon the arrival of the next pulse corresponding to the final value of the second information word set

on the control inputs of the comparison block 2.1, on the outputs of the first counting block 1.1, the second information word is set. This word enters the installation inputs of the first comparison block 2.1. As a result, a signal is generated at the output of the first comparison unit 2.1, which, through the first three-input element AND 9.1, which is probed by the following pulses from the output T, and the fourth two-input element OR 11.4, goes to the output 15 of the device.

The process of issuing the third and subsequent informational words at the exit

5 of the device is similar to that described;

The outputs 16 and 17 of the device control the indicator board, which inspects the operation of the device on the first iCHOBHOM counting channel or on the second iOM backup channel.

Consider the principle of operation of the circuit: ontrol, which follows the correct operation of the first calculating block 1.1.

Upon receipt of pulses from the output T, of the generator 12 pulses to the even input of the first counting unit 1.1, counting unit 1.1, it is filled with pulses at the outputs that enter the inputs of the multi-element element 7 of the digital structures of the MEC) pulses of long duration form on their) short-duration pulses the pulses from the odd outputs of the multi-element 7 digital structures are fed to the inputs of the first multiple input element OR 10.1, and from the emotic outputs to the inputs of the second input element OR 10.2. From the outputs of the first and second multi-input elements OR 10.1 and 10.2, these pulses arrive at the inputs of the first second two-input elements I .1 and 8.2, which, by controlling the signals coming from the outputs of the first 1K-trigger 5.1, output the impulse inputs first two-way entry OR 11.1

The first 1K-trigger 5.1, switch over the trailing edge of the pulses appearing from the output of the first two-way element OR 11.1, 40). Let, at a given moment in time, the next pulse, coming from the output T of the generator 12 of pulses, goes to the counting input of the first counting unit 1.1, which registers it on the falling front of this pulse, generating a signal on one of the odd outputs. This signal, the passage through the multipurpose element 7 of the digital structures, forms a pulse of short duration, which goes to one of the

It follows the tracking of the sequence of pulses from the outputs of the first even block 1.1.

The pulses from the output of the first IH 11.1 dual element are also fed to the R input of the second 1K trigger .2, which confirms the leading edge of the second 1K trigger 1 5.2 on the leading edge of the receiving pulse and returns it every time

this state until the signals from the first counting block 1.1 are inferior in strictly sequence definitions, since the 1K-trigger 5.2, controlled by the 1M front of the input pulses output / output from generator T 12 - (pulses at inputs I and clock input,

switch to one state.

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inputs of the first multi-input element OR 10.1, from the output of which it is fed to the input of the first two-input element AND 8.1, prepared for operation by a signal from the inverse output of the first 1K-trigger 5.1. From the output of the first two-input element AND 8.1 through the first two-input returns to the zero state before the arrival of the next pulse from the output T, because at this moment the leading edge of the next pulse coming from the output of the first two-input element OR 11.1 to the R input is already present The second IK-flip-flop 5.2, which returns the second J (-trigger 5.2 to the zero state. This allows the RS-flip-flop 6 to remain in zero state, which ensures the operation of the first channel (the first counting unit 1.1 and the first Second hand 2.1 comparison) h Res trehvhodovoy first AND gate 9.1 and the fourth two-input OR gate 15 to the output 11.4 of the device.

In case of violation of the sequence of pulse generation at the outputs of the multi-input elements OR 10.1 and 10.2, which is associated with failures in the operation of the first counting unit 1.1, it automatically switches to the second 5 channel (second counting unit 1.2 and second block 2.2 comparison) . This is provided by the RS-flip-flop 6, which, triggered, disconnects from the fourth two-input element OR 11.4 the first three-input element AND 9.1 and connects the second three-input element AND 9.2.

Consider the process of monitoring the operation of the first counting unit 1.1 5 and the moment when the device switches from the main channel (the first counting unit 1.1 and the first comparison block 2.1) to the backup channel (the second counting unit 1.2 and the second block 2.2 compare 40

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inputs of the first multi-input element OR 10.1, from the output of which it is fed to the input of the first two-input element AND 8.1, prepared for operation by a signal from the inverse output of the first 1K-trigger 5.1. From the output of the first two-input element And 8.1 through the first two-input 9

the first element OR 11.1 pulse arrives at the setup input R of the second 1K-flip-flop 5.2, on the leading edge of which the zero state of the second IK-flip-flop 5.2 is set, which was in the unit state at the time of the end of the previous input pulse coming from

output T, generator 12 pulses.

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As a result, the second 1K-trigger 5.2 remains in the zero state by the time of the arrival of the next pulse from the output Tj.

The impulse from the output of the first two-input element OR 11.1 is also fed to the clock input of the first IK-trigger 5.1, which is switched to one state on the falling edge of this pulse, prohibiting the operation of the first two-input element AND 8.1 and setting up for operation the second two-input element And 8.2. ,

In the pause between the pulses from the output T, the generator 12 pulses, pulses are generated from the output Tj of the generator 12 pulses shifted relative to the pulses from the output T by 1/2 period, which go to the I and clock inputs of the second hera 5.2, which is in the rear the front of this pulse is switched to a single state and remains there until the next pulse appears from the output T of the generator 12 pulses, on the falling front of which the first counting unit 1.1 registers it, forming a signal at one of the outputs that passes through the multi-purpose element NT 7 digital structures, one of the multi-input elements OR 10.1 or 10.2, two-input elements AND 8.1 or 8.2 and the first two-input element OR 1Т.1, enters the R input of the second 1K-flip-flop 5.2, which returns it to the zero state by the moment of arrival pulse output T generator 12 pulses. This blocks the operation of the third two-input element And 8.3, preventing the device from switching to the second, backup channel.

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and preparing for operation the first two-input element AND 8.1.

After the arrival of the T, third and fourth pulses through the previously described cycle, the first IK trigger 5.1 returns to its original, zero state.

The fifth pulse from the output T switches 10. the first 1K-trigger 5.1 in the single state, prohibiting the operation of the first two-input element And 8.4 and preparing for operation the second two-input element And 8.2.

Let the next pulse from the output T

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 enters the counting input of the first counting block 1.1, but the counting block 1.1 does not register. As a result, there is no signal at the next, even output of the first counting unit 1.1, and consequently, at the output of the second multi-input element OR 10.2. This will lead to the absence of a pulse at the output of the first two-input element OR 11.1. Consequently, the second 1K-trigger 5.2 remains in the single state and will prepare for operation the third two-input element AND 8.3, which after the arrival of the next pulse from the output T of the generator 12 of the pulses generates an output pulse, which through the third two-input element OR 11.3 goes to the S-input RS-flip-flop 6. On the leading edge of this pulse, RS-flip-flop 6 switches to one state, prohibits the operation of the first and third three-input elements AND 9.1 and 9.3 and enables the second three-input element AND 9.2, i.e. device switches to backup channel

(second calculating block 1.2, and second comparing block 2.2).

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Thus, due to the faulty-ti in the main channel (counting unit 1.1 and the first unit 2.1 of comparison), associated with the violation of the sequence of occurrence of pulses at the outputs of the multi-input elements OR 10.1 and 10.2, the device’s performance is not disturbed, since The main pulses arriving at the device output 15 are pulses coming from the output of the second three-input element AND 9.2.

According to the described cycle, the first 1K-trigger 5.1 switches to the zero state, prohibiting the operation of the second two-input element And 8.2

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Let the next pulse from the output T

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 enters the counting input of the first counting block 1.1, but the counting block 1.1 does not register. As a result, there is no signal at the next, even output of the first counting unit 1.1, and consequently, at the output of the second multi-input element OR 10.2. This will lead to the absence of a pulse at the output of the first two-input element OR 11.1. Consequently, the second 1K-trigger 5.2 remains in the single state and will prepare for operation the third two-input element AND 8.3, which after the arrival of the next pulse from the output T of the generator 12 of the pulses generates an output pulse, which through the third two-input element OR 11.3 goes to the S-input RS-flip-flop 6. On the leading edge of this pulse, RS-flip-flop 6 switches to one state, prohibits the operation of the first and third three-input elements AND 9.1 and 9.3 and enables the second three-input element AND 9.2, i.e. device switches to backup channel

(second calculating block 1.2, and second comparing block 2.2).

Thus, due to the faulty-ti in the main channel (counting unit 1.1 and the first unit 2.1 of comparison), associated with the violation of the sequence of occurrence of pulses at the outputs of the multi-input elements OR 10.1 and 10.2, the device’s performance is not disturbed, since The main pulses arriving at the output 15 of the device are pulses coming from the output of the second three-input element AND 9.2.

Consequently, normal operation of the device is ensured in the event of malfunctions in the main

channel associated with the exit from the string elements in the first counting unit 1.

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The process of issuing information layers

at the output of the device 15, when the backup kangle is operating, it is similar to the issue process when the main channel is operating.

Consider the principle of operation of the control circuit, which follows the correct operation of the first block 2.1 of comparison.

Since the third 1K-trigger 5.3 is in the initial, zero state, after the arrival of the trailing edge of the first pulse, coming from the output T, of the pulse generator 12, the third 1K-trigger 5.3 switches to the one state. As a result, the first group of information

the inputs of the switch 4 is connected to the outputs of the switch 4, on which the falling edge of the first pulse from the output T of the pulse generator 12 generates a code corresponding to the first input pulse fed to the first counting unit 1.1. Thus, at the installation and control inputs of the first block 1.1, an identical code is set. This, when the first comparison block 2.1 is operational, generates at its output a signal that arrives at the second input of the third three-input element And 9.3 From the output Tj of the pulse generator 12, an output pulse is generated on the output edge of which the third 1K-trigger 5.3 switches to the zero state, connecting the second group of information inputs to the outputs of the switch 4 and further to the control inputs of the first th block 2.1

Comparison, which provides comparison of 45 information inputs of the switch 4

codes from the outputs of the first counting unit 1.1 and the master unit 3. If they are equal, a signal is generated at the output of the first comparison unit 2.1, which after the comparison signal is missing, the second input element goes out to the second input of the first three And 9.1, which is a three-input element, and 9.3. This is because the arrival of the second pulse from the output prevents the passage of the next im T, the generator 12 of pulses forms the pulse from the output T of the generator 12 and the output pulse, which through the even-gg pulses through the third three-input true two-input element OR 11.4 element AND 9.3 and the second two-input arrives at the output 15 of the device and the OR element 11.2 to the clock input to the control input of the master block of the third 1K-trigger 5.3. As a result, 3, which is on the falling edge of this tata of this regular impulse, post0

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pulse at the outputs exposes the second information word.

In the case of non-comparison of the codes arriving at the first comparison block 2.1 from the outputs of the first counting block 1.1 and the master block 3, the pulse at the output of the first three-input element And 9.1 is absent. On the falling edge of the second pulse, coming from the output T of the generator of 12 pulses, the third 1K-flip-flop 5.3 switches to one state, and the first counting unit 1. 1 registers it, switching to the next state.

Switch 4 makes the connection of the first group of information inputs to the control inputs of the first comparison unit 2.1, which in the case of proper operation generates a signal at the output preparing the third three-input element AND 9.3 for operation. On the falling edge of the second pulse, coming from the output Tj of the generator 12 pulses through the third three-input element AND 9.3, the third 1K-flip-flop 5.3 switches to the zero state, connected to the outputs of the switch 4 to the second group of information inputs.

When the first block 2.1 compares correctly, the process of comparing the codes on the setup and control inputs that are connected to the first group of information inputs of the switch 4 in the single state of the third 1K flip-flop 5.3 is similar to the described cycle.

In case of malfunctioning of the first comparison unit 1.1 at its output at the time of comparing the code,

coming from the outputs of the first counting unit 1.1 through the first group

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on control inputs with a single state of the third 1K-flip-flop 5.3, with the code located on the setup inputs, at the output of the first block

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The generator of the 12 pulses coming from the output T, through the fourth two-input AND 8.4, prepared for operation by a signal from the direct output of the third 1K-flip-flop, and the third two-input element OR 8.3 to the S-input of the RS-flip-flop 6 It forbids operation of the first and third three-input elements of AND 9.1 and preparing the second three-input element of AND 9.2 for operation, which excludes the main channel and connects the backup channel to the output of the device.

In this way, the normal operation of the device is also ensured in the event of the failure of the first block 2. Comparison, which allows to carry out a full diagnostic work on checking the operability of the main channel (the first counting block 1.1 and the first block 2.1 comparison) and, in the event of a malfunction in it, allows automatic switching to the backup channel (second counting unit 1.2 and second comparison block 2.2).

The process of issuing information layers at the device output 15 when the backup channel is working (the second account and block 1.2 and the second comparison block 2.2 is similar to the process when the main channel is working (the first counting block 1.1 and the first comparison block 2.1).

Claims (1)

Invention Formula A counting device containing the first counting unit, the outputs of which are connected to the first group of information inputs of the switch and to the inputs of the multipurpose element of digital structures, the odd outputs of which are connected to the inputs of the first multi-input element OR, and the even outputs to the inputs of the second multiple input element OR , the output of the first multiple input element OR - with the first input of the first two-input element AND, the output of which is connected to one of the inputs of the first two-input element OR and with the 1 input of the first 1K trigger, inv The digital output of which is connected to the second input of the first two-input element AND, the output of the second multi-input element OR is connected to the first input of the second eleven of the two-input element AND, the output of the Co-Topoi o is connected to the second input of the first two-input element OR and to the K input of the first 1K flip-flop, the direct output of which is connected to the second input of the second two-input element OR, the output of the first two-input element OR is connected to the clock input of the first input A 1K flip-flop and an R-input of a second 1K-flip-flop, the forward output of which is connected to the first input of the third two-input element AND, the second counting unit, the driver unit, the comparison unit, the RS-trigger, the fourth two-input element AND, characterized in that for good In order to increase the reliability of the device, a pulse generator j is inserted in it, the second comparison unit, the third 1K-flip-flop, three two-input elements OR, the three three-input elements AND, while the outputs of the first counting unit are connected to the installation inputs of the first comparison unit, the outputs of the setting unit under- the keys to the control inputs of the second comparison unit and to the second group of information inputs of the switch, the outputs of which are connected to the control inputs of the first comparison unit, the outputs of the second counting unit are connected to The first inputs of the second comparator unit, the start bus is connected to the input of the pulse generator, the first output of which is connected to the counting inputs of the first and second counting units, with the first inputs of the first and second three-input elements And, with the first input of the fourth two-input element And OR, the second output of the pulse generator is connected to the first input of the third three-input element AND, with I and the clock inputs of the second IK-trigger, with the second input of the third two-input element And, the output of watts cerned two-input OR gate is connected to the clock input of the third flip-flop 1K, forward the output of which is connected to the control input of the switch and to the second input of the fourth two-input AND gate, the output the third two-input element And is connected to the first input of the third two-input element OR, the second input of which is connected to the output of the fourth two-input element And, and 13136898116 the output of the third two-input element-second input of the second two-input This OR is connected to the S-input of the RS-trig-element OR, the output of the first three-Vogoger, whose direct output is connected to the first to the second input of the third three-input input of the fourth two-input element of the AND, the output of the first OR block, the second input of which the comparison base is connected to the second input of the second input of the second and three input inputs of the first, and the third input of elements And, the third inputs of which are connected to the output of the second block are connected to the inverse output RS-Q of the comparison, the output of the fourth two-trigger trigger and connected to the K input of the secondary element OR is connected to a 1K-flip-flop trigger; the output of the third control input of the E-block of the blot-input element I is connected.