SU1508213A1 - Device for registering faults - Google Patents

Abstract

The invention relates to computing and can be used in devices for monitoring and troubleshooting. The purpose of the invention is to increase the speed of the device. The device contains a register 1, multiplexer 2, a group of multiplexers 3, the element OR 4, the clock generator 5, the element And 6, the counter 7, the element OR 8, the element AND-9, the counter 10, the multiplexer 11, the decoder 12, the element And 13 delay element 14, pulse shaper 15, register 16, trigger 17, elements OR NOT 18, 19, input 20 of the initial installation of the device, a group of information inputs 21 of the device, output 22 of the readiness of the device, a group of information outputs 23 of the device. The goal is achieved by introducing a second multiplexer, a group of multiplexers, a counter, a trigger, AND, AND-NOT, OR-NOT elements, as well as a new communication organization, which allows to increase the speed of failure detection by simultaneously controlling the group of input signals with subsequent determination signal numbers in the group. 1 il.

Description

SP

About 00

to

Ca

31508

The invention relates to computing and can be used in control and troubleshooting devices.

The purpose of the invention is to increase the speed of the device.

The device contains a register 1, multiplexer 2, group 3 multiplexers, the element OR 4, the generator 5 clock pulses, the element And 6, the counter 7, the element: FJIK 8, the element AND-9, the counter 10, the multiplexer 11 the decoder 12, the element And 13 , delay element 14, pulse generator 15, register 16, trigger 17, OR-NOT elements 18 and 19, device setup initial input 20, device information input group 21, device ready output 22 and device information output group 23.

The device works as follows.

After the initial setup signal arrives, trigger 17, register 1, multiplexer 2, counter 7, counter 10, and register 16 are reset to the initial state, and simultaneously counter 10 is started up. The monitored signals at the device inputs 21 are fed to the inputs of register 1. Received fault signals are fixed in register 1 and fed through multiplexer 2 to the inputs of multiplexers of group 3, which switch the states of the signal levels at the output of register 1. Each of the multiplexers of group 3 at a certain point in time, the strictly defined outputs of register 1 commute. The number of multiplexers in group 3 is chosen based on a given discrete step and the number of monitored channels and is defined as

“.,

where n is the number of controlled channels; .

k is the discrete step, any number from the row 1,2, ..., p, which determines the number of cycles in the polling cycle. It's obvious that . When one of the multiplexers of the group 3 malfunction signal appears at the output of the OR 4 element, a high level signal is generated, which through the OR 8 and

The NAND element 9 prohibits the operation of the counter 10. At the same time, the counter 7 is clocked with the clock frequency of the generator 5 and a write strobe enable signal is generated with a delay on the element 14. At the output of the counter 7, the addresses for the multiplexer 11 and the decoder 12 are generated, The multiplexer 11 performs a sequential polling of the outputs of the multiplexers of group 3, and the number of the channel to be determined is determined simultaneously in the decoder 12.

When a malfunction signal appears at the output of multiplexer 11, at the output of the And 13 element, a strobe is formed to write the number of the faulty channel to the register 16.

After the end of the polling of all multiplexers of group 3, a high-level signal appears at the output of the transfer of counter 7, triggering a single-oscillator 15, which generates a signal intended to control the operation of the trigger 17 to generate the set-up signals of register 1. The same the signal is used to increment the counter address unit. 10, wherein the counter 7 is reset. Multiplexers 3 select the next group of monitored channels.

Claims (1)

Invention Formula A device for fixing faults, containing the first and second registers, the first multiplexer, the first counter, two IPI elements, a clock generator, a pulse shaper and a delay element, the group of information inputs of the first register being a group of information inputs of the device, a group of information outputs of the second gistra A group of information outputs of the device, the first and second groups of outputs of the first register are connected respectively to the first and second groups of information inputs of the first mu The multiplexer, the group of information outputs of the first counter is connected to the first group of inputs of the decoder, characterized in that, in order to increase the speed of the device, a group of multi 5150 Plexors, the second multiplexer, the second counter, two OR-NOT elements, a trigger, two AND elements and the OR-NOT element, the groups of information inputs of the multiplexers are connected to the output group of the first multiplexer, the control input of which is combined with the first input of the first element OR-NOT and connected to the forward trigger output, the inverse output of which is connected to the first input of the second element OR NOT and with its own information input, the trigger input of the trigger is combined with the second inputs of the element OR NOT, to the first input of the element AND- NOT and connected to the pulse driver output, the input of which is connected to the output of the overflow signal of the first counter, the initial setup input of which is combined with the inputs of the initial setup and the first and second registers, the second counter i ger and connected to the input of the initial setup of the device, output the readiness of which is connected to the corresponding output of the second register, the group of information inputs of which is connected to the group of outputs of the decoder, the second group of information inputs of which are combined with the group the address inputs of the group multiplexers and connected to the output group of the second counter, the clock input of which is connected to the output of the NAND element, the second input of which is connected to the output of the first OR element, the first input of which is combined with the first input of the first AND element and connected to the output the second element OR, whose inputs are combined with the inputs of the second multiplexer and connected to the outputs of the corresponding multiplexers of the group, the group of address inputs of which is connected to the group of information outputs of the first counter, The current input of which is connected to the output of the first element I and to the input of the 3-hold element, the output of which is connected to the first input of the second element I, whose output is connected to the synchronization input of the second register, the output of the second multiplexer is connected to the second input of the second element I, the first and the second outputs of the clock pulse generator are connected to the second inputs of the first element AND the first element OR, respectively, the outputs of the first and second elements OR-NOT are connected respectively to the first and second installation inputs. Dami first register.