SU679984A1 - Shift register control unit - Google Patents

Description

(54) DEVICE FOR CONTROLLING REGISTER OF SHIFT

one

The invention relates to the field of computer technology and can be used to control computer nodes.

A device 1 is known that allows the shift register to be monitored by periodically diagnosing it with test combinations. The disadvantage of it is the considerable cost of equipment and the need for additional time for register diagnostics.

The closest to this technical solution is device 2, containing the first and second modulo-two adders, trigger, AND element, OR element, pulse shaper, first and second delay elements, OR element, AND element, the first input of the device being connected to the first the inputs of the first modulo-two adder and the monitored shift register; the second input of the device is connected to c: the pulse driver and the first delay element; the output of the latter is connected to the second input of the shift register and the input of the second element the delay, the output of which is connected to the primary; INPUT TERMINAL AND, OUTPUT

the shift register is connected to a group of outputs of the second adder modulo-two, the output of which is connected to the first inputs of the OR element, and a trigger, the second input of which is connected to the output of the driver, and Vssod with the second input of the first modulo-two adder, the output of which is connected to the second input of the OR element,

0, the output of which is connected to the second output of the AND element, the output of which is the output of the device.

The H-residue of such a device is a significant cost of equipment.

The aim of the invention is to reduce the amount of equipment.

This is achieved by the fact that the proposed device contains the second

Claims (1)

0 element And, the second input of the device is connected to the information input of the shift register and the second input, the trigger, the output of which is connected to the first input - - the first element of the AND, the output of the shift register is connected to the first input of the second element And, the output of the first modulo two connected to the first input of the second adder modulo two, the output of the gate driver is connected to the second inputs of the first and second elements I, whose outputs are connected to the second input of the first and second modulo adders two, respectively One of the latter is the output of the device. ya fig. 1 shows a block diagram of the proposed device; in fig. 2 time diagrams of his work. The device contains a gate driver 1, trigger 2, elements 3 and 4, a controlled register 5 shift clock bus b, bus 7 information signals and modulators two 8. and 9. The device works as follows. When the power is turned on, bus 6 receives clock pulses, and shift register 5 and trigger 2 come to state O on output, Strobe Former 1 outputs at its output a sequence of pulses whose duration is equal to clock pulses. The repetition period of these pulses is equal to the delay introduced by the shift register 5. When information signals appear on bus 7, a pulse from the output of the strobe generator 1 is another informational sign recorded on trigger 2 and stored there until the slug follow impulse comes from the stator 1 generator. The next strobe pulse is Wits when the output of the shift register 5 is Wits, the information recorded in Trigger 2 At the end of the next strobe pulse, Trigger 2 has a recorded information code, which takes place at the input of the shift register, etc. In this case, the outputs of the elements And 3 and 4 will take place, the same signals only if the shift register 5 is healthy. The signals from the outputs of the elements And are constantly fed to the inputs of two modulo-two adders and always the same during normal operation of the device, and the output of the adder modulo two 9 has a clock sequence of pulses, identical to the clock sequence received in the device via the bus b. When a malfunction appears in the device, the clock sequence at the output of the modulo two adder 9 is distorted, which serves as an error signal. In fact, the AND elements and the modulo two adder are a comparison circuit for each p bit of the input sequence that is remembered by trigger 2 the bit of the shift register is gated at the point in time when the given bit after the n shifts is in the last bit of the de register. The simplicity of the implementation of this logical function determines the reduction of equipment costs. The proposed device can be used to control shift registers of various lengths. For this, the gate driver must have as many exits as there are groups of registers of different lengths, and when ems, the gate driver equipment increases slightly. The remaining equipment increases in proportion to the number of monitored registers. Formula for controlling the register of shifts, containing a gate driver, a trigger, an element, the first and second modulo-two adders, the first input of the device is connected to a group of shift inputs of the controlled shift register and the first input of the first modulo-two adder, the gates of the gate generator are connected to the first input of the trigger, that is, in order to reduce the amount of equipment, it contains the second element I, the second input of the device connected to the information input of the shift register and the second m trigger input, the output of which is connected to the first input of the first element And, the output of the shift register is connected to the first input of the second element And, the output of the first modulo two adder is connected to the first input of the second modulo two, the output of the strobe generator is connected to the second inputs of the first and the second elements And, the outputs of which are connected to the second inputs of the first and second adders modulo two, respectively, and the output of the latter is the output device. Sources of information taken into account in the examination 1. USSR author's certificate No. 463973, class G 06 F 11/00, 1971, 2, USSR author's certificate No. 529488, class G 06 F 11/00, G 11 C 29 / 00, 1975, f-HILE n n n n P p p p p p p P STI {P PP 1 n n n n D) J- Mm n n n 022