RU1791806C - Generator of synchronizing signals - Google Patents

Abstract

The invention relates to digital technology, namely, pulse train generation devices, and can be used in control devices of automation and digital technology. The purpose of the invention is the expansion of functionality by changing the periods of the generated pulse sequences. A delay of 2T is introduced between the first and second pulses of the output sequences, which ultimately leads to an increase in the periods of all output sequences. Using the length indicator in this device (generator) allows you to control the time of periods of the generated pulse sequences, which allows you to control the time of machine cycles when used in digital information processing tools. The clock generator contains a clock generator, registers, elements I. 2 ill.

Description

The invention relates to the field of digital technology, in particular to pulse sequence generation devices, and can be used in control devices of automation and digital technology.

The purpose of the invention is to expand the functionality of the generator by changing the periods of the generated pulse sequences.

In FIG. 1 shows a block diagram of a clock generator; in FIG. 2 - time diagrams of his work.

The clock generator contains a clock 1, a first register 2, a first element And 3, a second element And 4, a second register 5, a third element And 6.

The inputs and outputs of the registers 2 and 5 are connected so that shift operations are performed according to clock pulses, which are supplied from the output of the generator 1 to the clock inputs of the registers 2 and 5, the second, third and fourth inverse outputs of the second register 5 go to the inputs of the third element And 6, the output of which is connected to the second input of the second register 5, and each direct output of the registers is connected to the previous input of this register, the first and second inverse outputs of the first register 2 are supplied to the inputs of the first element And 3 and through w The second element And 4 this signal is fed to the input of the second register 5.

The clock generator operates as follows.

-4 Yu

00 O O

The operation of the clock generator is based on the principle of a running unit, as a result of which the logic 1 signal appears alternately at the outputs of the second register 5 ’, as a result of which a pulse sequence is generated at each output with a period equal to K T, where T is the period of the triggering pulses generator 1; and K is the number of register exits. The enable signal is generated at the output of the third element And b if there are logical 1 at its inputs from the corresponding outputs of the second register 5, which physically means the absence of output pulses at the output of the clock generator, and is fed to the second input of the second register 5. According to the control pulse from the clock generator 1, this signal is recorded in the second register 5, as a result of which a logical 1 signal (Fig. 26) appears at its second output, which is supplied to its third input. On the next impulse of the generator. Logic 1 is set to the third output of the second register 5 (Fig. 2c), and the logical O signal is set to the second output, by the next control pulse the logical 1 signal is supplied to the fourth output of the second register 5 and removed from the third output. In this way, the output sequences of the pulses of the clock generator are generated.

If there is no sign of length (log. O) at the second input of the second element And 4 (Fig. 2e), a log is sent to the resetting input of the second register 5. 1 and the first register 2 does not affect the operation of the second register 5 and, accordingly, the temporal position of the generated output pulse sequences. The pulse period at each output of the second register 5 in this case is 4T. In this case, the temporary position of the pulses at the second output of the second register 5 and at the second output of the first register 2 (Fig. 2e) (i.e., at the additional output of the clock generator) coincides,

If there is a sign of length at the input of the clock generator (log. 1), the operation of the first register 2 affects the functioning of the output pulse sequences, for example, according to the clock pulse of the generator 1 after switching from the formation of the fourth output pulse (Fig. 2d) to the first (Fig. 2a) a log signal is set at the first inverse output of the first register 1. O, which, passing through elements 3 and 4, nullifies the second register 5, which also managed to generate a pulse of the first output sequence (Fig. 2a) at its first direct output, according to the next clock pulse of the generator 1, an additional output of the clock generator is generated

pulse (Fig. 2a), and the second register 5 is still zeroed, according to the third clock pulse, the first register 1 also appears in the zero state at the outputs, and through elements 3 and 4 at the resetting input

the second register 5 sets the log, 1, after which, for each clock pulse of the generator 1, the second, third, fourth and first pulses of the output sequences of the clock signals will be alternately generated at the outputs of the second register 5 (Fig. 2a-d). After that, the next pulse will be generated by the next clock pulse only at the second output of the first register 2 (Fig. 2e), and the pulse at the second output of the second register 5 will only appear after one clock of the generator 1.

The process continues.

So between the first and second

pulses of the output sequences of the clock signals (outputs of the second register 5) introduces a delay equal in duration to 2T, which ultimately leads to an increase in the periods of all

generated output sequences of clock signals. That is, using the length indicator in this device allows controlling the time of periods of the generated pulse sequences, which allows controlling the time of machine cycles in the digital information processing means used.

Claims (1)

The claims A clock generator comprising a clock generator, three AND elements and a first register, the clock input of which is connected to the output of the clock generator, characterized in that, for the purpose of expanding functionality by changing the periods of the generated pulse sequences, it contains a second register, the direct outputs of the first, second, third and fourth bits of which are the corresponding outputs of the clock generator, the direct outputs of the first and second bits of the first register are connected respectively to the input of the second bit of the first register and the fifth output of the clock generator, the inputs of the first bits of the first and second registers are connected to the direct output of the fourth bit yes of the second register, the direct outputs of the second and third bits of the second register are connected respectively with the inputs of the third and fourth bits of the second register, the inverse outputs of the second, third and fourth bits of which are connected to the inputs of the first element And, the output of which is connected to the input of the second bit yes the second register, the inverse outputs of the first and second bits of the first register are connected to the inputs of the second element And, the inverse output of which is connected to the first the input of the third element I. the second input of which is an input, indicating the period length of the clock generator, the clock input of the second register is connected to the output of the clock generator, the output of the third element And is connected to the reset input of the second register, the inverse reset input of the first register is connected to the unit bus potential of the clock generator.