SU752317A1 - Information input arrangement - Google Patents

Description

I

The invention relates to computing and can be used in automated control systems (ACS) operating in the time division mode.

A device for controlling information transmission is known, consisting of a clock generator, a clock pulse generator, micro-operations triggers and information registers, the clock pulse generator being connected to the clock generator and micro-operations triggers that are connected to the information registers l.

In this device, the shift and transmission of the single and zero bits of information is carried out at the clock frequency, i.e. the single and zero bits of information are transmitted aa the same period of time. Because of this, the device has significant drawbacks of limited speed and complexity.

The closest to the proposed technical solution is an interface device containing an information register, three flip-flops, two AND elements, two OR elements, two counters, a driver for five common pulses, a clock generator, and the output of the first OR element is connected to the first input of the first trigger output Which is connected to the first inputs of the first and second elements And 2.

The disadvantage of this device lies in its complexity and high equipment costs.

The purpose of the invention is to reduce the appliance costs.

The goal is achieved by the fact that a device containing a counter, an information register, three triggers, two OR elements, two AND elements and a clock generator, the output of the first OR element is connected to the first input of the first trigger, the output of which is connected to the first inputs of the first and second And elements, the first inputs of the information register and the second trigger are respectively the first and second inputs of the device, three AND elements, a trigger and an OR element are introduced, with the first and second outputs of the information register The country is connected respectively to the second codes of the first and second elements AND, the third inputs of which are connected to the first output of the clock generator, and the outputs to the corresponding inputs of the second element, OR, the output connected to the second inputs of the first trigger and information register and the counter input , the output of which is connected to the second input of the second trigger, the output of the third element And and the first input of the second trigger are connected to the corresponding inputs of the first element OR, the second output of the sync pulse generator owls are connected to the first inputs of the fourth and fifth And elements, the outputs of which are the first and second outputs of the device, respectively; the output and the first input of the third trigger are connected respectively to the second input and output of the fourth And element, and the second input to the output of the second And element, the outputs of the first and fourth elements AND are connected to the corresponding inputs of the third element OR, the output connected to the first input of the fourth trigger, the output of which is connected to the second input of the fifth element AND, and the second input from the first th input of the third AND gate and the output of the fifth AND gate, the second flip-flop output coupled to a second input of the third element I.

The drawing shows the block diagram of the device.

The device contains a generator of blue sync pulses, an information register 2, a shift shaping unit 3, a code issuing unit 4, inputs 5 and 6 and outputs 7 and 8 of the device, elements 9 "13 AND, elements 14-16 OR, counter 17, triggers 18-21 ,

The generator 1 clock pulses emits pulses from the wallpaper. exits one often ™. you, but shifted each relative aruga.

The information register 2 is used to record information therein from input 5, to store and output it to block 3, which generates shifts in shear pulses, which occur at its second input.

The shift shaping unit 3 is designed to generate shift pulses according to the signal of the beginning of the transmission and the signals of the end of the transmission of the information code. Block 3 consists of elements 9-11 and elements 14 and 15 OR, counter 17, and triggers 18 and 19.

The code issuing unit 4 encodes each bit of information followed by issuing its code to outputs 7 and 8, as well as generating and issuing a signal that the transmission of the information code has been completed. Block 4 consists of elements 12 and 13 AND, element 16 OR and triggers 2О and 21,

The device works as follows

The code is transmitted in two stages; writing a code followed by 1 shift of information by one bit and issuing a code of a bit of information and a signal that the code has been transmitted. These micro-operations are performed | at the same frequencies, but shifted in time relative to each other.

The first shift pulse is generated when a signal is received that permits the transfer, and each subsequent pulse is generated by the signal of the end of the transmission of the next code of the information bit.

The zero bit of information is transmitted by one pulse on output 8 (zero bit code), and the single bit is transmitted by two pulses on two outputs 7 and 8 (single bit code), with output 8 being common for transmitting the zero and single bit codes information.

The operation of the device begins when a signal arrives at the input 6 allowing the transfer of information. Trigger 10 is switched by this signal and one bit of information is output in accordance with the potentials that come from the first and second outputs of information register 2, to the code output unit 4 at the clock frequency from the first output of the generator 1. At the same time, unit 3 generates ONE shift pulse, which arrives at the second input of the information register, shift information by one bit.

The second inputs of elements 9 and 10, respectively, arrive at a unit to zero potentials from the output of information register 2. The clock pulses arriving at the third inputs of these elements AND are blocked by a signal fed to their first inputs from a single output of trigger 18 (control). The transmission enable signal from input 6 enters the installation in one state of the trigger 19 and through element 14 OR to the installation of the trigger 18. The high potential from the single output of the trigger 19 opens element 11 AND to pass from output 8 the end of the transmission of the transmission of the information code. Element 11 and open; the entire transmission and is closed by a low potential from the single output of the trigger 19 when it is set to the zero state by an overflow signal from the counter 17. A high potential from the single output and the trigger 18 (control) opens the elements 9 and 10 I. At the output of one of these elements on whits im pulse. For example, if a high potential is applied to the second input of element 9 I, m, that is, a single bit of information must be transmitted, then an output appears at the output of this element, which switches the trigger 20 and simultaneously through element 15 OR sets the trigger 18 in the zero state, thereby prohibiting the passage of sync pulses through elements 9 and 10 I. This same pulse arrives at the input of the counter 17, intended for counting the number of pulses and producing an overflow signal when the last shift pulse arrives, and It also enters the second input of the information register 2.

When transmitting the zero bit of information, the signal from the output of element 10 AND switches trigger 21 through element 16 OR and is fed to the input of element 15 OR, the signal from the output of which, as before, is fed to the inputs of counter 17, trigger 18 and information register 2. End signal transmitting the information code through the element 11 AND and the element 14 OR enters the single input of the trigger 18 and sets it to the single state. The high potential from a single output of the trigger 18 permits the passage of the next pulse through the elements 9 and 10 I.

All subsequent bits of information are transmitted in the same way as described above.

After the last shift pulse has been issued, counter 17 outputs the sig Formula of the invention.

A device for entering information containing a counter, an information register, three triggers, two OR elements, two AND elements and a clock generator, the output of the first OR element connected to the first input of the first trigger, the output of which is connected to the first inputs of the first and second elements And, the first the inputs of the information register and the second trigger are, respectively, the first and second inputs of the device, characterized in that, in order to reduce hardware costs, three AND elements, a trigger and an IL element are introduced into the device And, the first and second outputs of the information register are connected respectively to the second inputs 76 of the overflow to the installation in the zero state of the trigger 19, the low potential, from a single output of which prohibits the passage of the signal of the transmission of the information code transmission through the element 11 I. through the element 16 OR, arrives at the single input of the trigger 21 and sets it to the single state. A high potential from the single output of the trigger 21 opens element 13 and the sync pulses from the second input of the generator 1 arrive at output 8 (output; code of the zero bit of information). At the same time, this signal enters the input of the trigger 21, sets it to the zero state and thereby closes the element 13 I. In the case of receiving a signal of a single bit of information, the trigger 20 is set to one and allows the signal to pass through the element 12 And to output 7, set to zero state of trigger 20 and through element 16 OR to set to single state of trigger 21. High potential from single output of trigger 21 allows the next clock pulse to pass through element 13. And on exit 8, the signal is set Ack to zero state of trigger 21 and signal to terminate the transmission of the information code. Thus, the device transmits information using less equipment as compared to the known.

the first and second elements of AND, the third codes of which are connected to the first clock of the clock generator, and the outputs to the corresponding inputs of the second OR element, the output connected to the second inputs of the first trigger and information register and the counter input, the output of which is connected to the second input of the second trigger , the output of the third element And the first input of the second trigger is connected to the corresponding inputs of the first element OR, the second output of the clock generator is connected to the first inputs of the fourth and fifth element ntov And, the outputs of which are respectively the first and second outputs The DVR, output and first input of the third flip-flop are respectively connected to the second input and output chetvertbgo

And, the second input - with the output of the second element And, the outputs of the first and fourth elements And connected to the corresponding inputs of the third element OR, the output connected to the first input of the fourth trigger, the output of which is connected to the second input of the fifth element And, and the second input - with the first input of the third element And and the output of the fifth element And, the output of the second trigger is connected to the second input of the third element I.

Sources of information taken into account in the examination

1. USSR author's certificate No. 432484, class, G 06 G 5/00, 1972,

2. USSR author's certificate according to the application of the Ministry of Health 26О5677 / 18-24,

cl. Q 06 P 3/04, 03/14/78 (prototype).

Claims (1)

Claim A device for inputting information comprising a counter, an information register, three triggers, two OR elements, two AND elements and a clock generator, the output of the first OR element being connected to the first input of the first trigger, the output of which is connected to the first inputs of the first and second AND elements, the first the inputs of the information register and the second trigger are respectively the first and second inputs of the device, characterized in that, in order to reduce hardware costs, three elements And, a trigger and an OR element, are entered into the device, p Therefore, the first and second outputs of the information register are connected respectively to the second inputs' 7 of the first AND second AND elements, the third inputs of which are connected to the first output of the clock generator, and the outputs are connected to the corresponding inputs of the second OR element, the output connected to the second inputs of the first trigger and the information register and the counter input, the output of which is connected to the second input of the second trigger, the output of the third element And and the first input of the second trigger are connected to the corresponding inputs of the first element OR, the second output of the clock generator is connected to the first inputs of the fourth and fifth elements of And, the outputs of which are the first and second outputs of the device, the output and the first input of the third trigger are connected respectively to the second input and output of the fourth element And, and the second input to the output of the second element AND, the outputs of the first and fourth elements AND are connected to the corresponding inputs of the third 5 OR gate connected to the first input of the fourth trigger, the output of which is connected to the second input of the fifth AND element, and the second input to the first input of the third AND element, and 0 the output of the fifth AND element, the output of the second trigger is connected to the second input of the third AND element .