SU997256A1 - Pulse frequency converter - Google Patents

Description

The goal is achieved by the fact that the device containing the delay line, the group of elements AND, the first inputs of which are connected to the first outputs of the code setting block, and the outputs - to the inputs of the OR element, whose output is the output of the device, is additionally entered the group of elements 11, the element OR, a trigger and a matching element, the output of which is connected to the input of the delay line, the first input is the input of the device, and the second input is connected to the output of the trigger, the first input of which is connected to the first output of the delay line and the second input The first element of the AND group of elements is And, the second input of the trigger is connected to the output of the additional element OR, the inputs of which are connected to the outputs of the elements AND of the additional groups of elements AND, the first inputs of which are connected to the corresponding second outputs of the block for setting the code, the second inputs of the elements of the additional group of elements And connected to the corresponding outputs, starting from the second, the delay line and to the second inputs of the elements AND the main group of elements I.

FIG. 1 shows a block diagram of the device; in fig. 2 cyclograms explaining the operation of the device ...

The device contains a coincidence element 1, a delay line 2, a code setting block .3, elements 4-7 AND the basic group, element 8 OR, elements 9-11 AND the additional group, element 12 OR, and trigger 13.

The device operates as follows. In the initial position, the trigger 13 issues an enabling signal to element 1. The first input frequency pulse passes to the delay line 2, appears after some time at its first output and triggers the trigger 13, which removes the enabling signal from element 1 and this prohibits the passage of subsequent pulses, the input frequency to the delay line 2. As the pulse moves further along the delay line, it appears in turn at all of its outputs and hits elements 4-7 AND, then element 8 OR and exit t pulses only through those elements 4-7 AND, to which the enabling signals from block 3 are fed. Thus, the code of block 3 determines the order of the signals at the output of the device. The impulse to reset the trigger 13 comes through element 12 OR from one of the elements 9-11 And, which is selected by block 3. After resetting, trigger 13 returns to the initial state and sends a disrupting signal to coincidence element 1 to skip the next input frequency pulse to delay line 2

Thus, the main group of elements And forms the order of the pulses at the output beyond the time-delay pulse at the input, and the additional group of elements And, controlled by the trigger 13f, forms this delay time. Based on the required frequency multiplication factor, block 3 gives permissive signals to the elements AND of both groups, determines the period of the following pulses at the output and the corresponding delay of the pulses at the input. The selection of the discreteness of the delay line determines the constancy of the pulse following period at the output for any multiplication factor.

FIG. 2a, S, and S are given the time diagrams of the example of the device in the modes, respectively, multiplier, frequency divider, and pulse trainer, where the letters Z, dJ and e indicate the signals at the device input, the trigger output, and the device output, respectively.

FIG. 2a and during time T, determined by the cocked trigger state (Fig. 2C1, () j, 4 impulses arrived at the input (Fig. 2a, -2,), and twelve impulses from the delay line passed to the output (Fig. 2 0 , 6). Frequency change factor

., 12 .. - l, 3,

those. device is working

as a frequency multiplier.

FIG. 2 iJ during this time 4 impulses arrived at the input, and only 3 passed at the output. The frequency change frequency in this case

K.-t .0.75, i.e. device operation.

melts as a frequency divider.

In both cases, the pulse period at the output is constant and maintained with the accuracy provided by the delay line. And in the known device, the period is changed 2 times.

Claims (3)

FIG. 2 shows the time diagram of the device operation in the pulse shaper mode. During the time T on the output of the device, there was a series of 7 pulses, unevenly located within the period of the Perio.d series, in this example, is equal to the TRs considered in FIG. 2 examples of frequency conversion are given for the same run time of trigger 3, but by the command of block 3 it is possible to change the reset time of trigger 13 and thereby change time T, i.e. influence the change in the frequency conversion ratio or set a different period of the pulse train. Resetting flip-flop 13 triggers a pulse from the input to line 2 of the delay. Therefore, in contrast to the known device, no shapers and M-pulses are necessary in this device. In order to obtain a longer or shorter pulse duration, it is necessary to reset the flip-flop 13, respectively, to the second, third outputs or to the delay line input. In the proposed device, for a time equal to the input frequency, the output can be obtained by the number of pulses retention line delay, and in the known - only one. Thus, the device has wider functionality, as it gives to the output. The constant period of pulses does not require shapers of the duration of the output pulses, extends the frequency multiplying limits and can work in the mode of frequency divider and shaper of the series of pulses. Invention A pulse frequency converter containing a delay line, a group of elements a whose first inputs are connected to The first outputs of the code setting block are the outputs. - with the inputs of the OR element, the output of which is the output of the device, o, TL, which means that, in order to expand its functionality, a group of AND elements, an OR element, a trigger and a coincidence element, an output that is connected, are added to it to the input of the delay line, the first input is the input of the device, and the second input is connected to the trigger output, the first input of which is connected to the first output of the line delay and the second input of the first element of the AND group of elements, the second input of the trigger is connected to the output of the auxiliary An OR element whose inputs are connected to the outputs of elements AND of an additional group of elements AND, the first inputs of which are connected to the corresponding second outputs of the code entry block, the second inputs of elements AND of an additional group of elements AND are connected to the corresponding outputs, starting with the second, the delay line and the second inputs elements And the main group of elements I. Sources of information taken into account during the examination 1. USSR author's certificate No. 526071, cl. H 03 K 5 / -156, 1976. 2. Authors certificate of the USSR 473389, cl. H 03 K 5/156, 1975. 3. Authors certificate of the USSR 365823, cl. H 03 K 23/00, 1973. . "T f J e ,. allllish 1shshshshshiglschsch LT " 9 p n p 9 # jmfl jinjL e u and