SU363207A1 - - Google Patents

Description

CODE CONVERTER - TIME INTERVAL

one

The invention relates to a pulsed technique and can be applied in various automatic control systems.

Known converter circuits are code-time interval in which the unit increment method is used. They contain a pulse generator, a counter, a decryption circuit and logic elements controlling the account.

A code inverse to the source code is entered into the counter of the converter. After the arrival of the start of the conversion, impulses from the generator begin to arrive at the counter.

The counter works on the addition until a bullet code appears on it, then the high-order counter of the counter generates an overflow pulse, marking the end of the time interval.

However, for such converters, the code-time interval is characterized by a large conversion error, which also changes during operation.

The aim of the invention is to increase the accuracy of the converter.

To do this, in the proposed invention between the coincidence circuit and the trigger, the delay element and the two-input element “AND” are connected in series, the second input of which is connected to the inverse output of the pulse generator, and the input of the frequency divider is connected to the inverse output of the pulse generator.

FIG. 1 shows a block diagram of a converter; in fig. 2 shows timing diagrams for p-code 2; To division 3. The converter consists of a generator /

pulses, an AND 2 element, a pulse counter 3, an account control trigger 4, a frequency divider 5, an encoder 6, a matching circuit 7, a delay element 8, an AND 9 element and a key 10.

In the initial state, the counter 3 of the converter is reset to a null and the trigger 4 of the account control closes the AND 2 circuit. The generator 1 generates pulses (see Fig. 2 a), which are output to the And 2 element and

a frequency divider circuit 5 producing a clock start-pulse of a short duration when the trailing edge of the pulse appears at the direct output of the generator / at time intervals somewhat larger than the maximum possible specified intervals (see Fig. 2b).

The time interval is set using a code that is entered by connecting the corresponding bits of the binary counter 3 to

Scheme 7 is the same.

When key 10 is opened, the first clock start-up pulse opens element "AND 2, and pulses from generator 1 are output to binary counter 3, which works to add up to the appearance of unit potentials on all outputs of the counting triggers connected to the coincidence circuit (see FIG. . 2d. The coincidence circuit works (see Fig. 2, (3).

To eliminate the intersection of the trailing edge of the pulse received from the inverted output of the generator 1 and the leading edge of the pulse from the coincidence circuit 7, when counter 5 is connected to the last initial stages (which may trigger the “9” element from the leading edge of the last counting pulse), the coincidence output signal is delayed by delay element 8, but with the restriction that the total delay (/ transfer delay t + delay delay) be less than the duration of the counting pulse (Fig. 2e).

The signal from coincidence circuit 7, delayed by delay element 8, prepares an AND 9 circuit during a pause at the inverted output of generator 1, but it opens with a leading edge of the pulse, which corresponds to the falling edge of the last counting pulse, i.e. 1. The counter 3 is reset to zero, and the pulse of the end of the time interval stops counting by closing the element “AND 2” (see Fig. 2).

Thus, the beginning and end of reference are carried out in the period of the appearance of the trailing edge of the pulse at the direct output of the generator.

In the next conversion cycle, all processes are repeated.

Subject invention

Converter code is a time interval containing a pulse generator, the direct output of which is connected to one input of the AND element, another input of which is connected to the output of the control trigger, and the output of the element of AND is connected to the input of the counter, the outputs of which through an encoder are connected to the inputs matches, a frequency divider, the output of which is connected to the first control trigger input, characterized in that, in order to increase accuracy, it contains an additional element "AND", one input of which is connected via a delay line to the output of the coincidence circuit, another input is connected to the inverse output of the pulse generator, which is connected to the input of the frequency divider, the output of the additional element "AND is connected to the second input of the control trigger.

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